# US 10,121,861 B2 · Nanowire transistor fabrication with hardmask layers

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- Number: US 10,121,861 B2
- Document ID: US10121861B2
- Status: Granted
- Kind: B2
- Application number: 13/996,850
- Filed: 2013-03-15
- Published: 2015-05-14
- Granted: 2018-11-06
- Earliest claimed: 2013-03-15
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Seung Hoon Sung; Seiyon Kim; Kelin Kuhn; Willy Rachmady; Jack Kavalieros
- Web page: https://patentgrep.com/patent/US10121861B2

## CPC

- H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)}
- B41F 3/46: Details
- B41F 17/08: for printing on filamentary or elongated articles, or on articles with cylindrical surfaces
- B41N 10/04: multi-layer
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- B41N 2210/04: Intermediate layers
- B41N 2210/14: characterised by macromolecular organic compounds
- Y10T 156/10: Methods of surface bonding and/or assembly therefor
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B41F: PRINTING MACHINES OR PRESSES (manifolding devices or office printing machines B41L)
- B41N: PRINTING PLATES OR FOILS (photosensitive material G03); MATERIALS FOR SURFACES USED IN PRINTING MACHINES FOR PRINTING, INKING, DAMPING, OR THE LIKE; PREPARING SUCH SURFACES FOR USE AND CONSERVING THEM
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- Y10T: TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION

## Abstract

A nanowire device of the present description may be produced with the incorporation of at least one hardmask during the fabrication of at least one nanowire transistor in order to assist in protecting an uppermost channel nanowire from damage that may result from fabrication processes, such as those used in a replacement metal gate process and/or the nanowire release process. The use of at least one hardmask may result in a substantially damage free uppermost channel nanowire in a multi-stacked nanowire transistor, which may improve the uniformity of the channel nanowires and the reliability of the overall multi-stacked nanowire transistor.

## Claims

### Claim 1

A nanowire transistor, comprising:
a plurality of nanowire channels formed above a microelectronic substrate, wherein the plurality of the nanowire channels are spaced apart from one another; wherein one nanowire channel of the plurality of nanowire channels is positioned farther from the microelectronic substrate than the remainder of the plurality of nanowire channels;
a source abutting a first end of each nanowire channel of the plurality of nanowire channels;
a drain abutting a second end of each nanowire channel of the plurality of nanowire channels;
a first spacer positioned proximate the first end of each nanowire channel of the plurality of nanowire channels and a second spacer positioned proximate the second end of each nanowire channel of the plurality of nanowire channels, wherein the first spacer physically contacts each nanowire channel of the plurality of nanowire channels and wherein the second spacer physically contacts each nanowire channel of the plurality of nanowire channels;
a hardmask layer comprising a first hardmask portion and a second hardmask portion, wherein an entirety of the hardmask layer is formed above the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, wherein a hardmask material of the hardmask layer and a spacer material of the first spacer and the second spacer are different and selectively removable with respect to each other; and
a gate dielectric material abutting a top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, wherein the gate dielectric material is positioned between the first hardmask portion and the second hardmask portion;
wherein the first hardmask portion abuts the first spacer, abuts the source, abuts the gate dielectric material, and abuts the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, such that the first hardmask portion covers a portion of the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels between the source and the gate dielectric material, such that the first hardmask portion extends between the gate dielectric material and the first end of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, and separates the first spacer from the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, and wherein the second hardmask portion abuts the second spacer, abuts the drain, abuts the gate dielectric material, and abuts the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, such that the second hardmask portion covers another portion of the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels between the drain and the gate dielectric material, such that the second hardmask portion extends between the gate dielectric material and the second end of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels, and separates the second spacer from the top surface of the one nanowire channel of the plurality of nanowire channels farther from the microelectronic substrate than the remainder of the plurality of nanowire channels.

### Claim 2 (depends on 1)

The nanowire transistor of claim 1, further including a gate electrode material abutting the gate dielectric material.

### Claim 3 (depends on 1)

The nanowire transistor of claim 1, wherein the first hardmask portion and the second hardmask portion comprise a material selected from the group consisting of silicon, porous silicon, amorphous silicon, silicon nitride, silicon oxynitride, silicon oxide, silicon dioxide, silicon carbonitride, silicon carbide, aluminum oxide, hafnium oxide, zirconium oxide, tantalum silicate, lanthanum oxide, and polymer materials.

### Claim 4 (depends on 1)

The nanowire transistor of claim 1, wherein the plurality of nanowire channels comprise silicon germanium.

### Claim 5 (depends on 1)

The nanowire transistor of claim 1, wherein the plurality of nanowire channels comprise silicon.

### Claim 6 (depends on 1)

The nanowire transistor of claim 1, wherein the source and the drain comprise n-doped silicon.

### Claim 7 (depends on 1)

The nanowire transistor of claim 1, wherein the source and the drain comprise p-doped silicon.

### Claim 8 (depends on 1)

The nanowire transistor of claim 1, wherein the source and the drain comprise p-doped silicon germanium.

### Claim 9 (depends on 1)

The nanowire transistor of claim 1, wherein the gate dielectric material comprises a material selected from the group consisting of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium oxide, and lead zinc niobate.

### Claim 10 (depends on 2)

The nanowire transistor of claim 2, wherein the gate electrode material comprises a material selected from the group consisting of titanium, tungsten, tantalum, aluminum, copper, ruthenium, cobalt, chromium, iron, palladium, platinum, molybdenum, manganese, vanadium, gold, silver, niobium, and alloys thereof.

### Claim 11 (depends on 2)

The nanowire transistor of claim 2, wherein the gate electrode material comprises a metal carbide.

### Claim 12 (depends on 11)

The nanowire transistor of claim 11, wherein the metal carbide comprises a material selected from the group consisting of titanium carbide, zirconium carbide, tantalum carbide, and tungsten carbide.

### Claim 13 (depends on 2)

The nanowire transistor of claim 2, wherein the gate electrode material comprises a metal oxide.