# US 10,121,859 B2 · Method of manufacturing semiconductor devices with transistor cells and semiconductor device

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- Number: US 10,121,859 B2
- Document ID: US10121859B2
- Status: Granted
- Kind: B2
- Application number: 15/457,833
- Filed: 2017-03-13
- Published: 2017-09-21
- Granted: 2018-11-06
- Earliest claimed: 2016-03-17
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Ravi Keshav Joshi; Johannes Baumgartl; Oliver Blank; Oliver Hellmund; Martin Poelzl
- Web page: https://patentgrep.com/patent/US10121859B2

## CPC

- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- B81B 3/0072: {For controlling internal stress or strain in moving or flexible elements, e.g. stress compensating layers}
- B81B 7/008: {MEMS characterised by an electronic circuit specially adapted for controlling or driving the same (B81B7/0087 takes precedence; arrangements for starting, regulating, braking, or otherwise controlling an actuator H02N; control arrangements or circuits for visual indicators G09G3/00)}
- B81C 1/00246: {Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate}
- G01P 15/125: by capacitive pick-up
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/60: Insulated-gate field-effect transistors [IGFET] (H10D30/40 takes precedence)
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D 62/00: Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/142: {Anode regions of thyristors or collector regions of gated bipolar-mode devices}
- H10D 62/154: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10D 64/112: {comprising multiple field plate segments}
- H10D 64/117: {Recessed field plates, e.g. trench field plates or buried field plates}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- B81B 2207/015: the micromechanical device and the control or processing electronics being integrated on the same substrate
- B81C 2203/0707: Monolithic integration, i.e. the electronic processing unit is formed on or in the same substrate as the micromechanical structure
- G01C 19/5719: using planar vibrating masses driven in a translation vibration along an axis
- G01C 19/5783: Mountings or housings not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
- H10D 12/211: {Gated diodes}
- H10D 64/256: {for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies (source or drain electrodes of TFTs H10D30/673)}
- H10P 72/7416: {used during dicing or grinding}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B81B: MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES (piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/00, H10N35/00)
- B81C: PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS (making microcapsules or microballoons B01J13/02; processes or apparatus specially adapted for the manufacture or treatment of piezoelectric, electrostrictive or magnetostrictive elements per se H10N30/01)
- G01P: MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT (measuring or recording blood flow A61B5/02, A61B8/06; monitoring speed or deceleration of electrically-propelled vehicles B60L3/00; vehicle lighting systems adapted to indicate speed B60Q1/54; determining position or course in navigation, measuring ground distance in geodesy or surveying G01C; combined measuring devices for measuring two or more variables of movement G01C23/00; measuring velocity of sound G01H; measuring velocity of light G01J7/00; measuring direction or velocity of solid objects by reception or emission of radiowaves or other waves and based on propagation effects, e.g. Doppler effect, propagation time, direction of propagation, G01S; measuring speed of nuclear radiation G01T; measuring acceleration of gravity G01V; {measuring or recording the speed of trains B61L23/00; speed indicators incorporated in motor vehicles B60K35/00; measuring frequency or phase G01R; traffic control G08G})
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G01C: MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY (measuring liquid level G01F; radio navigation, determining distance or velocity by use of propagation effects, e.g. Doppler effects, propagation time, of radio waves, analogous arrangements using other waves G01S)

## Abstract

First reinforcement stripes are formed on a process surface of a base substrate. A first epitaxial layer covering the first reinforcement stripes is formed on the first process surface. Second reinforcement stripes are formed on the first epitaxial layer. A second epitaxial layer covering the second reinforcement stripes is formed on exposed portions of the first epitaxial layer. Semiconducting portions of transistor cells are formed in or portions of micro electromechanical structures are formed from the second epitaxial layer.

## Claims

### Claim 1

A semiconductor device comprising:
transistor cells comprising body regions that form first pn junctions with a drift structure in a semiconductor portion;
first reinforcement stripes in the semiconductor portion, wherein first longitudinal axes of the first reinforcement stripes are parallel to a first surface of the semiconductor portion; and
second reinforcement stripes between the first reinforcement stripes and the first surface, wherein second longitudinal axes of the second reinforcement stripes are parallel to the first surface,
wherein the second longitudinal axes are orthogonal to the first longitudinal axes.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the second longitudinal axes are tilted to the first longitudinal axes.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the body regions of the transistor cells form second pn junctions with source regions formed between the first surface and the body regions.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a separation section of the drift structure separates the first and second reinforcement stripes.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein an intermediate section of the semiconductor portion separates the first reinforcement stripes from a second surface of the semiconductor portion opposite to the first surface.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the first and second reinforcement stripes comprise at least one of silicon oxide, silicon nitride, silicon carbide, diamond-like carbon, and a metal inert against silicon.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein a width of the first and second reinforcement stripes is in a range from 50 μm to 500 μm.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, wherein the first and second reinforcement stripes extend through a central portion of the semiconductor portion.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the first and second reinforcement stripes spare a central portion of the semiconductor portion.

### Claim 10 (depends on 1)

The semiconductor device of claim 1, wherein at least the first or the second reinforcement stripes have a uniform center-to-center distance.

### Claim 11

A micro electromechanical device comprising:
a micro electromechanical structure formed in a semiconductor portion;
first reinforcement stripes in the semiconductor portion, wherein first longitudinal axes of the first reinforcement stripes are parallel to a first surface of the semiconductor portion; and
second reinforcement stripes between the first reinforcement stripes and the first surface, wherein second longitudinal axes of the second reinforcement stripes are parallel to the first surface,
wherein the second longitudinal axes are orthogonal to the first longitudinal axes.

### Claim 12 (depends on 11)

The micro electromechanical device of claim 11, wherein the second longitudinal axes are tilted to the first longitudinal axes.

### Claim 13

A method of manufacturing a semiconductor device, the method comprising:
forming first reinforcement stripes on a process surface of a base substrate;
forming a first epitaxial layer on the process surface, the first epitaxial layer covering the first reinforcement stripes;
forming second reinforcement stripes on the first epitaxial layer;
forming a second epitaxial layer on exposed portions of the first epitaxial layer, the second epitaxial layer covering the second reinforcement stripes;
forming semiconducting portions of transistor cells in or portions of micro electromechanical structures from the second epitaxial layer; and
removing at least a portion of the base substrate from a side opposite to the first epitaxial layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the first and second reinforcement stripes comprise at least one of silicon oxide, silicon nitride, diamond-like carbon, silicon carbide, and a metal inert against silicon.

### Claim 15 (depends on 13)

The method of claim 13, wherein second longitudinal axes of the second reinforcement stripes are tilted to first longitudinal axes of the first reinforcement stripes.

### Claim 16 (depends on 13)

The method of claim 13, wherein forming semiconducting portions of the transistor cells comprises forming body regions that form first pn junctions with a drift structure in the second epitaxial layer and second pn junctions with source regions formed in the second epitaxial layer between a main surface and the body regions.

### Claim 17

A method of manufacturing a semiconductor device, the method comprising:
forming dicing stripes on a process surface of a base substrate;
forming an epitaxial layer on the process surface, the epitaxial layer covering the dicing stripes;
forming semiconducting portions of transistor cells in portions of micro electromechanical structures from the epitaxial layer;
forming dicing trenches in a vertical projection of the dicing stripes and separating semiconductor portions of semiconductor dies;
attaching an auxiliary carrier at a front side opposite to the base substrate;
removing the base substrate; and
separating the semiconductor dies by at least partially removing the dicing stripes.

### Claim 18 (depends on 17)

The method of claim 17, further comprising filling the dicing trenches with a sacrificial material before attaching the auxiliary carrier.

### Claim 19 (depends on 17)

The method of claim 17, wherein the dicing stripes taper with increasing distance to the process surface.

### Claim 20 (depends on 17)

The method of claim 17, further comprising:
recessing, selectively against the dicing stripes, a surface of the epitaxial layer exposed by removing the base substrate; and
forming, after removing the base substrate, a back side metallization on an exposed surface of the epitaxial layer.

### Claim 21 (depends on 20)

The method of claim 20, wherein tapering protruding portions of the dicing stripes shadow edge portions of the recessed surface of the epitaxial layer.

### Claim 22 (depends on 21)

The method of claim 21, further comprising isotropically etching, after forming the back side metallization, exposed edge portions of the recessed epitaxial layer, wherein the dicing stripes are lifted off.