# US 10,121,858 B2 · Elongated semiconductor structure planarization

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- Number: US 10,121,858 B2
- Document ID: US10121858B2
- Status: Granted
- Kind: B2
- Application number: 14/927,822
- Filed: 2015-10-30
- Published: 2017-05-04
- Granted: 2018-11-06
- Earliest claimed: 2015-10-30
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Richard Kenneth Oxland; Blandine Duriez; Mark van Dal; Martin Christopher Holland
- Web page: https://patentgrep.com/patent/US10121858B2

## CPC

- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- B82Y 10/00: Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/125: {Shapes of junctions between the regions}
- H10D 64/01: Manufacture or treatment
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/016: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 84/8311: {the IGFETs characterised by having different channel structures}
- H10P 14/271: {characterised by the preparation of substrate for selective deposition}
- H10P 14/272: {using mask materials other than SiO2 or SiN}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3421: {Arsenides}
- H10P 14/3422: {Antimonides}
- H10P 14/3462: {Nanowires}
- H10P 52/402: {of semiconductor materials}
- H10P 52/403: {of conductive or resistive materials}
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- B82Y: SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

According to one example, a method includes epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate. The method further includes forming a gate layer on the substrate, the gate layer contacting the elongated semiconductor structures. The method further includes performing a planarization process on the gate layer and the elongated semiconductor structures, and epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions.

## Claims

### Claim 1

A method comprising:
epitaxially growing first portions of a plurality of elongated semiconductor structures on a semiconductor substrate, the elongated semiconductor structures running perpendicular to the substrate;
forming a gate layer on the substrate, the gate layer being formed over the elongated semiconductor structures;
performing a planarization process on the gate layer and the elongated semiconductor structures;
after the planarization process, recessing the gate layer; and
epitaxially growing second portions of the plurality of elongated semiconductor structures, the second portions comprising a different material than the first portions, wherein junctions between the first portions and the second portions are offset from an edge of the gate layer.

### Claim 2 (depends on 1)

The method of claim 1, further comprising, forming the offset by recessing the first portions of the plurality of elongated semiconductor structures after the planarization process.

### Claim 3 (depends on 1)

The method of claim 1, further comprising:
forming a first dielectric layer over the second portions of the plurality of elongated semiconductor structures;
performing a chemical mechanical polishing process on the first dielectric layer to planarize the first dielectric layer and the second portions of the plurality of elongated semiconductor structures; and
forming a second dielectric layer over the first dielectric layer.

### Claim 4 (depends on 1)

The method of claim 1, further comprising, replacing the gate layer with a metal gate layer.

### Claim 5 (depends on 1)

The method of claim 1, further comprising, before growing the first portions of the elongated semiconductor structures, forming polish-stop pillars on the substrate.

### Claim 6 (depends on 5)

The method of claim 5, wherein the polish-stop pillars comprise varying heights at different regions of the substrate.

### Claim 7 (depends on 1)

The method of claim 1, wherein the first portions of the elongated semiconductor structures comprise a first conductivity type, the method further comprising:
after the planarization process, removing a subset of the first portions of the elongated semiconductor structures to form trenches; and
forming third portions of the elongated semiconductor structures within the trenches, the third portions comprising a second conductivity type is different from the first conductivity type.

### Claim 8 (depends on 1)

The method of claim 1, wherein the first portions and the second portions each have a height within a range of about 4-50 nanometers.

### Claim 9 (depends on 1)

The method of claim 1, wherein the gate layer has a height within a range of about 5-100 nanometers.

### Claim 10 (depends on 1)

The method of claim 1, wherein junctions between the first portions and the second portions are offset from an edge of the gate layer within a range of about 0-50 nanometers.

### Claim 11 (depends on 1)

The method of claim 1, wherein the elongated semiconductor structures comprise one of: a nanowire or a nanobar.

### Claim 12 (depends on 1)

The method of claim 1, wherein the first portions and the second portions comprise at least one of: silicon (Si), germanium (Ge), silicon germanium (SiGe), indium arsenide (InAs), indium gallium arsenide (InGaAs), indium antimonide (InSb), or indium gallium antimonide (InGaSb).

### Claim 13 (depends on 1)

The semiconductor device of claim 1, wherein forming the offset comprises selectively etching the first portions.

### Claim 14 (depends on 1)

The semiconductor device of claim 1, wherein forming the offset comprises selectively etching the gate layer.

### Claim 15

A method comprising:
forming a first set of elongated semiconductor structures on a semiconductor substrate, the first set of elongated semiconductor structures running perpendicular to the substrate;
forming a dummy gate layer on the substrate, the dummy gate layer being formed over the first set of elongated semiconductor structures;
performing a planarization process on the dummy gate layer and the first set of elongated semiconductor structures; and
forming, a second set of elongated semiconductor structures on and aligned with the first set of elongated semiconductor structures, the second set of elongated semiconductor structures comprising a different material than the first set of elongated semiconductor structures.

### Claim 16 (depends on 15)

The method of claim 15, wherein the planarization process comprises a chemical mechanical polishing (CMP) process.

### Claim 17 (depends on 15)

The method of claim 15, wherein forming the first set of elongated semiconductor structures and forming the second set of elongated semiconductor structures comprises an epitaxial growth process.