# US 10,121,857 B2 · Nano-tube MOSFET technology and devices

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- Number: US 10,121,857 B2
- Document ID: US10121857B2
- Status: Granted
- Kind: B2
- Application number: 14/702,592
- Filed: 2015-05-01
- Published: 2016-11-03
- Granted: 2018-11-06
- Earliest claimed: 2008-12-31
- Assignees: Alpha and Omega Semiconductor Incorporated
- Applicants: Alpha and Omega Semiconductor Incorporated
- Inventors: Hamza Yilmaz; Daniel Ng; Lingping Guan; Anup Bhalla; Wilson Ma; Moses Ho; John Chen
- Web page: https://patentgrep.com/patent/US10121857B2

## CPC

- H10D 62/122: {oriented at angles to substrates, e.g. perpendicular to substrates}
- H10D 8/00: Diodes (variable-capacitance diodes H10D1/64; gated diodes H10D12/00)
- H10D 8/60: Schottky-barrier diodes
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 12/441: {Vertical IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 30/0291: {of vertical DMOS [VDMOS] FETs}
- H10D 30/0297: {using recessing of the gate electrodes, e.g. to form trench gate electrodes}
- H10D 30/831: {Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202)}
- H10D 62/111: {Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs}
- H10D 62/137: {Collector regions of BJTs}
- H10D 62/154: {Dispositions}
- H10D 62/157: {Impurity concentrations or distributions}
- H10D 62/158: {Dispositions}
- H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)}
- H10P 52/402: {of semiconductor materials}
- H10D 30/051: {of FETs having PN junction gates (H10D30/015 takes precedence)}
- H10D 30/66: Vertical DMOS [VDMOS] FETs
- H10D 30/665: {having edge termination structures}
- H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

This invention discloses a semiconductor power device disposed in a semiconductor substrate and the semiconductor substrate has a plurality of trenches. Each of the trenches is filled with a plurality of epitaxial layers of alternating conductivity types constituting nano tubes functioning as conducting channels stacked as layers extending along a sidewall direction with a “Gap Filler” layer filling a merging-gap between the nano tubes disposed substantially at a center of each of the trenches. The “Gap Filler” layer can be very lightly doped Silicon or grown and deposited dielectric layer. In an exemplary embodiment, the plurality of trenches are separated by pillar columns each having a width approximately half to one-third of a width of the trenches.

## Claims

### Claim 1

A method for manufacturing a metal oxide semiconductor field effect
transistor (MOSFET) comprising:
opening a plurality of deep trenches between lightly doped pillars and substantially filling the deep trench with alternating N and P doped multiple epitaxial layers overflowing and covering a top surface of the semiconductor substrate with a top epitaxial layer wherein the epitaxial layers form charge balanced nano tubes for functioning as conducting channels extending along a sidewall direction; and
forming a body region encompassing source region surrounding a gate of the MOSFET disposed near a top surface of the pillar comprising the volume of the semiconductor substrate for conducting a current through the nano tubes to a drain region disposed on the bottom of the semiconductor substrate.

### Claim 2 (depends on 1)

The method of claim 1 further comprising a step of:
filling a remaining central gap with a gap filler.

### Claim 3 (depends on 2)

The method of claim 2 wherein:
said step of filling said central gap with said gap filler further comprising a step of forming said gap filler as a lightly doped silicon with a dopant concentration equal to or less than 10% of a dopant concentration of adjacent nano tubes.

### Claim 4 (depends on 2)

The method of claim 2 wherein:
said step of filling said central gap with said gap filler further comprising a step of forming an oxide layer to fill said central gap.

### Claim 5 (depends on 2)

The method of claim 2 wherein:
said step of filling said central gap with said gap filler further comprising a step of depositing a dielectric layer in said central gap.

### Claim 6 (depends on 2)

The method of claim 2 further comprising:
removing the epitaxial layer from a top surface down to original Pillar surface by a CMP (Chemical Mechanical Polishing) process and growing an N-epitaxial layer with a thickness substantially between 1 to 5 microns.