# US 10,121,855 B2 · Stacked nanowire semiconductor device

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- Number: US 10,121,855 B2
- Document ID: US10121855B2
- Status: Granted
- Kind: B2
- Application number: 15/177,483
- Filed: 2016-06-09
- Published: 2017-07-06
- Granted: 2018-11-06
- Earliest claimed: 2016-01-05
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Michael A. Guillorn; William L. Nicoll; Hanfei Wang
- Web page: https://patentgrep.com/patent/US10121855B2

## CPC

- H10D 62/121: {oriented parallel to substrates}
- H10D 30/0193: {by modifying properties of the stacked channels}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/506: {having different thicknesses, sizes or shapes}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6713: {characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes}
- H10D 30/6729: {characterised by the electrodes}
- H10D 30/673: {characterised by the shapes, relative sizes or dispositions of the gate electrodes}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10D 64/015: {removing at least parts of gate spacers, e.g. disposable spacers}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/83: of only insulated-gate FETs [IGFET]
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10D 88/01: {Manufacture or treatment}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.

## Claims

### Claim 1

A semiconductor device comprising:
a stack of nanowires, the stack including:
a first nanowire having a first length;
a second nanowire having a second length, the second nanowire arranged above the first nanowire, the first length being greater than the second length; and
a third nanowire having a third length, the third nanowire arranged above the second nanowire, the third length being different from the first and second lengths;
a gate stack arranged over channel regions of the first nanowire, the second nanowire, and the third nanowire;
a first source/drain region attached on ends of the first nanowire;
a second source/drain region attached on ends of the second nanowire;
a third source/drain region attached on ends of the third nanowire, wherein the first source/drain region, the second source/drain region and the third source/drain region are formed of different materials;
a spacer formed on a portion of top surfaces of each of the first, second, and third nanowires, continuing in between a portion of each of the first, second, and third nanowires, and continuing on a portion of bottom surfaces of each of the first, second, and third nanowires.

### Claim 2 (depends on 1)

The device of claim 1, wherein the second nanowire has a length greater than a length of the third nanowire.

### Claim 3 (depends on 1)

The device of claim 1, wherein:
the first source/drain region is arranged on the first nanowire;
the second source/drain region is arranged on the second nanowire; and
the third source/drain region is arranged on the third nanowire.

### Claim 4 (depends on 1)

The device of claim 1, wherein the first nanowire, the second nanowire, and the third nanowire include a semiconductor material.