# US 10,121,853 B2 · Structure and process to tuck fin tips self-aligned to gates

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- Number: US 10,121,853 B2
- Document ID: US10121853B2
- Status: Granted
- Kind: B2
- Application number: 15/794,636
- Filed: 2017-10-26
- Published: 2018-03-01
- Granted: 2018-11-06
- Earliest claimed: 2015-05-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Bruce B. Doris; Hong He; Sivananda K. Kanakasabapathy; Gauri Karve; Fee Li Lie; Derrick Liu; Soon-Cheon Seo; Stuart A. Sieg
- Web page: https://patentgrep.com/patent/US10121853B2

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure is provided that includes a semiconductor fin portion having an end wall and extending upward from a substrate. A gate structure straddles a portion of the semiconductor fin portion. A first set of gate spacers is located on opposing sidewall surfaces of the gate structure; and a second set of gate spacers is located on sidewalls of the first set of gate spacers. One gate spacer of the second set of gate spacers has a lower portion that directly contacts the end wall of the semiconductor fin portion.

## Claims

### Claim 1

A method of forming a semiconductor structure, the method comprising:
forming a gate structure straddling a portion of a semiconductor fin,
providing a first set of gate spacers on opposing sidewalls of the gate structure and straddling another portion of the semiconductor fin;
forming a sacrificial dielectric liner over the first set of gate spacers and the gate structure and straddling a remaining portion of the semiconductor fin;
forming a patterned material stack having an opening;
cutting the semiconductor fin utilizing the patterned material stack, a portion of sacrificial dielectric liner within the opening and one gate spacer of the first set of gate spacers as an etch mask to provide a semiconductor fin portion containing the gate structure and having an exposed end wall;
performing a lateral etch to pull back the expose end wall of the semiconductor fin portion underneath or aligned to a sidewall of the one gate spacer of the first set of gate spacers within the opening; and
forming a second set of gate spacers, wherein one gate spacer of the second set of gate spacers contains a lower portion that directly contacts the exposed end wall of the semiconductor fin portion.

### Claim 2 (depends on 1)

The method of claim 1, wherein a portion of the opening exposes a portion of the sacrificial dielectric liner over the semiconductor fin.

### Claim 3 (depends on 2)

The method of claim 2, wherein prior to cutting the semiconductor fin, an etch is performed to remove the exposed portion of the sacrificial dielectric liner over the semiconductor fin.

### Claim 4 (depends on 1)

The method of claim 1, wherein each gate spacer of the first set of gate spacers straddles over the semiconductor fin portion, and wherein another gate spacer of the second set of gate spacers straddles another portion of the semiconductor fin portion.

### Claim 5 (depends on 1)

The method of claim 1, wherein the gate structure is a functional gate structure.

### Claim 6 (depends on 1)

The method of claim 1, wherein the gate structure is a sacrificial gate structure, and wherein the sacrificial gate structure is replaced with a functional gate structure after forming the first and second sets of gate spacers.

### Claim 7 (depends on 1)

The method of claim 1, wherein providing the first set of gate spacers comprises depositing a dielectric material and performing a spacer etch.

### Claim 8 (depends on 1)

The method of claim 1, wherein the sacrificial dielectric liner is composed of a dielectric material that has a different etch rate than a dielectric material that provides the first set of gate spacers.

### Claim 9 (depends on 1)

The method of claim 1, wherein the patterned material stack comprises, from bottom to top, an optical planarization material and an antireflective coating.

### Claim 10 (depends on 1)

The method of claim 1, further comprising removing the patterned material stack after cutting the semiconductor fin.

### Claim 11 (depends on 1)

The method of claim 1, wherein the cutting the semiconductor fin comprises an anisotropic etch.

### Claim 12 (depends on 1)

The method of claim 1, wherein the lateral etch comprises a wet isotropic chemical etch.

### Claim 13 (depends on 1)

The method of claim 1, wherein the lateral etch comprises a dry isotropic chemical etch.

### Claim 14 (depends on 1)

The method of claim 1, wherein remaining portions of the sacrificial dielectric liner are removed prior to forming the second set of gate spacers.

### Claim 15 (depends on 1)

The method of claim 1, wherein the first and second sets of gate spacers are composed of a same dielectric material.

### Claim 16 (depends on 1)

The method of claim 1, wherein the first set of gate spacers is composed of a dielectric material that differs from the dielectric material that provides the second set of gate spacers.

### Claim 17 (depends on 1)

The method of claim 1, wherein the second set of gate spacers is formed by deposition of a dielectric material and performing a spacer etch.