# US 10,121,851 B2 · Fin recess last process for FinFET fabrication

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- Number: US 10,121,851 B2
- Document ID: US10121851B2
- Status: Granted
- Kind: B2
- Application number: 15/063,224
- Filed: 2016-03-07
- Published: 2016-06-30
- Granted: 2018-11-06
- Earliest claimed: 2012-11-09
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Kuo-Cheng Ching; Shi Ning Ju; Guan-Lin Chen
- Web page: https://patentgrep.com/patent/US10121851B2

## CPC

- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 62/314: {having vertical doping variations (vertical IGFETs H10D30/63)}
- H10D 62/832: being Group IV materials comprising two or more elements, e.g. SiGe
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/514: {characterised by the insulating layers}
- H10D 84/834: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method includes forming isolation regions extending from a top surface of a semiconductor substrate into the semiconductor substrate, and forming a hard mask strip over the isolation regions and a semiconductor strip, wherein the semiconductor strip is between two neighboring ones of the isolation regions. A dummy gate strip is formed over the hard mask strip, wherein a lengthwise direction of the dummy gate strip is perpendicular to a lengthwise direction of the semiconductor strip, and wherein a portion of the dummy gate strip is aligned to a portion of the semiconductor strip. The method further includes removing the dummy gate strip, removing the hard mask strip, and recessing first portions of the isolation regions that are overlapped by the removed hard mask strip. A portion of the semiconductor strip between and contacting the removed first portions of the isolation regions forms a semiconductor fin.

## Claims

### Claim 1

A device comprising:
isolation regions; and
a Fin Field-Effect Transistor (FinFET) comprising:
a semiconductor fin between two opposite portions of the isolation regions, wherein the semiconductor fin protrudes higher than top surfaces of the isolation regions;
a gate dielectric on sidewalls of the semiconductor fin;
a gate electrode over the gate dielectric; and
a gate spacer on a sidewall of the gate dielectric, wherein a portion of the gate spacer is at a same level as a portion of the semiconductor fin, wherein the gate dielectric comprises a portion between and contacting the gate electrode and the gate spacer, and wherein a bottom surface of the gate dielectric is higher than a bottom surface of the gate spacer.

### Claim 2 (depends on 1)

The device of claim 1 further comprising an isolation region comprising:
a first portion overlapped by a portion of the gate electrode, wherein the gate dielectric contacts a first top surface of the first portion of the isolation region; and
a second portion on a side of, and physically joined to, the first portion, wherein a second top surface of the second portion of the isolation region is higher than the first top surface of the first portion of the isolation region.

### Claim 3 (depends on 1)

The device of claim 1 further comprising an isolation region comprising:
a first portion overlapped by a portion of the gate electrode, wherein the gate dielectric contacts a first top surface of the first portion of the isolation region; and
a second portion on a side of, and physically joined to, the first portion, wherein a second top surface of the second portion of the isolation region is lower than the first top surface of the first portion of the isolation region.

### Claim 4 (depends on 3)

The device of claim 3, wherein the gate spacer comprises a first bottom surface contacting the second top surface of the second portion of the isolation region.

### Claim 5 (depends on 3)

The device of claim 3, wherein the gate spacer further comprises a second bottom surface contacting a top surface of the semiconductor fin.

### Claim 6 (depends on 3)

The device of claim 3, wherein the gate spacer comprises a sidewall contacting a sidewall of the first portion of the isolation region.

### Claim 7 (depends on 3)

The device of claim 3 further comprising an Inter-Layer Dielectric (ILD), wherein a bottom portion of the ILD is lower than a bottommost surface of the gate dielectric.

### Claim 8 (depends on 3)

The device of claim 3 further comprising an Inter-Layer Dielectric (ILD), wherein a portion of the ILD is lower than a top portion of the first portion of the isolation region.

### Claim 9 (depends on 1)

The device of claim 1, wherein the semiconductor fin comprises a relaxed silicon germanium region, and an additional semiconductor region over the relaxed silicon germanium region, and wherein the additional semiconductor region has a germanium percentage different from a germanium percentage in the relaxed silicon germanium region.

### Claim 10 (depends on 9)

The device of claim 9, wherein the germanium percentage of the additional semiconductor region is higher than the germanium percentage in the relaxed silicon germanium region.

### Claim 11

A device comprising:
a Fin Field-Effect Transistor (FinFET) comprising:
a semiconductor fin;
an isolation region on a side of the semiconductor fin, wherein the semiconductor fin is higher than the isolation region;
a gate dielectric on sidewalls and a top surface of the semiconductor fin, wherein the gate dielectric overlaps the isolation region;
a gate electrode over a bottom portion of the gate dielectric, wherein a sidewall of the gate electrode contacts a sidewall portion of the gate dielectric; and
a gate spacer comprising:
a first portion laterally overlapping the semiconductor fin; and
a second portion laterally overlapping the isolation region, wherein a sidewall of the second portion of the gate spacer is in physical contact with a sidewall of the isolation region, and a bottom surface of the second portion of the gate spacer is lower than a top surface of the isolation region.

### Claim 12 (depends on 11)

The device of claim 11 further comprising an Inter-Layer Dielectric (ILD) contacting the gate spacer, wherein the ILD extends lower than a bottommost surface of the gate dielectric.

### Claim 13 (depends on 11)

The device of claim 11 further comprising an Inter-Layer Dielectric (ILD) contacting the gate spacer, wherein a portion of the ILD is lower than the top surface of the isolation region.

### Claim 14

A device comprising:
a Fin Field-Effect Transistor (FinFET) comprising:
a semiconductor fin;
an isolation region on a side of the semiconductor fin, wherein the semiconductor fin is higher than the isolation region, and the isolation region comprises a first portion and a second portion;
a gate dielectric on sidewalls and a top surface of the semiconductor fin, wherein the gate dielectric overlaps the first portion of the isolation region, and a sidewall of a sidewall portion of the gate dielectric contacts a sidewall of the second portion of the isolation region;
a gate electrode over a bottom portion of the gate dielectric, wherein a sidewall of the gate electrode contacts the sidewall portion of the gate dielectric; and
a gate spacer comprising:
a first portion overlapping the semiconductor fin; and
a second portion overlapping the second portion of the isolation region, and
an Inter-Layer Dielectric (ILD) contacting the gate spacer, wherein a top surface of the first portion of the isolation region is higher than a bottom surface of a portion of the ILD.

### Claim 15 (depends on 14)

The device of claim 14, wherein a bottom surface of the second portion of the gate spacer is higher than a top surface of the first portion of the isolation region.

### Claim 16 (depends on 14)

The device of claim 14, wherein a portion of the gate electrode is lower than a top portion of the second portion of the isolation region.

### Claim 17 (depends on 14)

The device of claim 14, wherein a portion of the gate dielectric is lower than a bottom surface of the ILD.

### Claim 18 (depends on 14)

The device of claim 14, wherein a bottom end of the gate spacer is level with a bottom surface of the ILD.

### Claim 19 (depends on 1)

The device of claim 1, wherein a top surface of the gate dielectric is level with a top surface of the gate spacer.

### Claim 20 (depends on 11)

The device of claim 11, wherein a top surface of the gate dielectric is level with a top surface of the gate spacer.