# US 10,121,850 B2 · Power semiconductor device and method of fabricating the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,850 B2 - Document ID: US10121850B2 - Status: Granted - Kind: B2 - Application number: 15/612,683 - Filed: 2017-06-02 - Published: 2017-12-07 - Granted: 2018-11-06 - Earliest claimed: 2016-06-03 - Assignees: Hyundai Autron Co., Ltd. - Applicants: Hyundai Autron Co., Ltd. - Inventors: Young Joon Kim; Hyuk Woo; Tae Yeop Kim; Han Sin Cho; Tae Young Park; Ju Hwan Lee - Web page: https://patentgrep.com/patent/US10121850B2 ## CPC - H10D 62/107: {Buried supplementary regions, e.g. buried guard rings (multi-RESURF H10D62/111)} - H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs} - H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs} - H10D 62/106: {having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions} - H10D 62/112: {for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers} - H10D 62/393: {Body regions of DMOS transistors or IGBTs (cell layout of DMOS H10D62/127)} - H10W 10/031: {of isolation regions comprising PN junctions} - H10W 10/30: Isolation regions comprising PN junctions - H10D 64/111: {Field plates} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Provided is a power semiconductor device comprising a gate electrode in a trench of a substrate; a body region having a first conductivity type on one side of the gate electrode; a source region having a second conductivity type adjacent to the gate electrode; a floating region having a first conductivity type on the other side of the gate electrode; an edge doped region having a first conductivity type spaced apart from the floating region and electrically connected to the source region; an edge junction isolation region having a second conductivity type between the floating region and the edge doped region; and a drift region having a second conductivity type below the floating, edge doped, and edge junction isolation regions, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region. ## Claims ### Claim 1 A power semiconductor device comprising: a gate electrode disposed in a trench of a substrate; a body region having a first conductivity type disposed on one side of the gate electrode in the substrate; a source region having a second conductivity type disposed adjacent to the gate electrode in the body region having a first conductivity type; a floating region having a first conductivity type disposed on the other side of the gate electrode in the substrate; an edge doped region having a first conductivity type spaced apart from the floating region having a first conductivity type and electrically connected to the source region in the substrate; an edge junction isolation region having a second conductivity type interposed between the floating region having a first conductivity type and the edge doped region having a first conductivity type in the substrate; and a drift region having a second conductivity type disposed below the floating region having a first conductivity type, the edge doped region having a first conductivity type, and the edge junction isolation region having a second conductivity type, wherein the doping concentration of a second conductivity type in the edge junction isolation region is higher than the doping concentration of a second conductivity type in the drift region. ### Claim 2 (depends on 1) The device of claim 1, wherein the edge doped region having a first conductivity type is disposed in an edge termination region of the device. ### Claim 3 (depends on 1) The device of claim 1, further comprising: a wiring pattern disposed on the substrate to electrically connect the source region and the edge doped region having a first conductivity type. ### Claim 4 (depends on 1) The device of claim 1, wherein the floating region having a first conductivity type surrounds the bottom surface and at least the other side of the gate electrode, wherein the maximum doping depth of the floating region having a first conductivity type is larger than the depth of the trench, and wherein the maximum doping depth of the edge doped region having a first conductivity type is larger than the depth of the trench. ### Claim 5 (depends on 4) The device of claim 4, wherein, in a vertical distribution of the electric field from an upper surface of the substrate through a region between the floating region having a first conductivity type and the edge doped region having a first conductivity type to a lower surface of the substrate, a depth at which a maximum electric field is located is larger than the depth of the trench. ### Claim 6 (depends on 1) The device of claim 1, wherein the substrate includes a wafer and an epitaxial layer grown on the wafer, and wherein a region below the floating region having a first conductivity type and a region below the edge doped region having a first conductivity type include a boundary surface between the wafer and the epitaxial layer. ### Claim 7 (depends on 1) The device of claim 1, wherein the second conductivity type and the first conductivity type have opposite conductivity types and are each one of n-type and p-type. ### Claim 8 A method for fabricating a power semiconductor device, the method comprising: implanting impurities having a first conductivity type into a first region and a second region on a wafer; implanting impurities having a second conductivity type, which have a higher doping concentration than that of the impurities having a second conductivity type in the wafer, into a third region disposed between the first region and the second region; forming a substrate by forming an epitaxial layer on the wafer, the substrate comprising the wafer and the epitaxial layer; forming a floating region having a first conductivity type in the substrate corresponding to the first region, an edge doped region having a first conductivity type in the substrate corresponding to the second region, and an edge junction isolation region having a second conductivity type in the substrate corresponding to the third region, by diffusing the impurities; forming a source region having a second conductivity type by implanting impurities into the epitaxial layer and diffusing the impurities; and forming a wiring pattern for electrically connecting the source region and the edge doped region. ### Claim 9 (depends on 8) The method of claim 8, wherein a region below the floating region having a first conductivity type and a region below the edge doped region having a first conductivity type include a boundary surface between the wafer and the epitaxial layer.