# US 10,121,847 B2 · Galvanic isolation device

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- Number: US 10,121,847 B2
- Document ID: US10121847B2
- Status: Granted
- Kind: B2
- Application number: 15/462,741
- Filed: 2017-03-17
- Published: 2018-09-20
- Granted: 2018-11-06
- Earliest claimed: 2017-03-17
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Benjamin Stassen Cook; Barry Jon Male; Robert Alan Neidorff
- Web page: https://patentgrep.com/patent/US10121847B2

## CPC

- H10D 1/692: {Electrodes}
- H10W 44/20: at high-frequency [HF] or radio frequency [RF]
- H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)}
- H10W 70/465: {Bumps or wires}
- H10W 90/811: {Multiple chips on leadframes}
- H10W 72/07554: {changes in dispositions}
- H10W 72/536: {the connected ends being ball-shaped}
- H10W 72/547: {Dispositions of multiple bond wires}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

## Claims

### Claim 1

A galvanic isolation device comprising:
a first integrated circuit (IC) die having a top surface, an opposite bottom surface, and a side surface therebetween;
a first communication circuit formed in a circuit layer of the first IC die;
a first conductive plate formed on the first IC die proximate the top surface, the first conductive plate being coupled to the first communication circuit;
a dielectric isolation layer positioned on top of a portion of the top surface of the first IC die, such that the dielectric isolation layer completely covers the first conductive plate;
a second conductive plate juxtaposed with the first conductive plate but separated from the first conductive plate by the dielectric isolation layer, such that the first conductive plate and the second conductive plate form a capacitor, the second conductive plate being arranged for coupling to a second communication circuit;
a second IC die having a circuit layer in which the second communication circuit is formed; and
a conductive isolated region formed in the second IC die such that the conductive isolated region is dielectrically isolated from the circuit layer of the second IC die;
the second conductive plate being formed by the conductive isolated region of the second IC die and coupled to the second communication circuit.

### Claim 2 (depends on 1)

The device of claim 1, in which the first communication circuit is an RF receiver having an input coupled to the first conductive plate.

### Claim 3 (depends on 1)

The device of claim 1, in which the second communication circuit is an RF transmitter having an output coupled to the second conductive plate.

### Claim 4 (depends on 1)

The device of claim 1, in which the dielectric isolation layer is arranged to withstand a voltage differential of at least 20 kv between the first conductive plate and the second conductive plate.

### Claim 5 (depends on 1)

The device of claim 1, in which the dielectric isolation layer includes at least two insulating layers.

### Claim 6 (depends on 1)

The device of claim 1, in which the dielectric isolation layer extends beyond a portion of the side surface of the first IC die and also extends beyond a portion of a side surface of the second IC die.

### Claim 7 (depends on 1)

The device of claim 1, in which the first conductive plate is a metallic plate formed in a metal interconnect layer of the first IC die.

### Claim 8 (depends on 1)

The device of claim 1, in which the dielectric isolation layer is a polymer film.

### Claim 9 (depends on 1)

The device of claim 1, in which the dielectric isolation layer includes a non-conductive silicon compound.

### Claim 10 (depends on 1)

The device of claim 1, in which the dielectric isolation layer includes a plurality of layers.

### Claim 11 (depends on 10)

The device of claim 10, in which the dielectric isolation layer includes a metal layer between the plurality of layers.

### Claim 12

A galvanic isolation device comprising:
a first integrated circuit (IC) die having a top surface, an opposite bottom surface, and a side surface therebetween;
first communication circuitry formed in a circuit layer of the first IC die;
first conductive plates formed on the first IC die proximate the top surface, the first conductive plates being coupled to the first communication circuitry;
a dielectric isolation layer positioned on top of a portion of the top surface of the first IC die, such that the dielectric isolation layer completely covers the first conductive plates;
second conductive plates juxtaposed with the first conductive plates but separated from the first conductive plates by the dielectric isolation layer, such that the first conductive plates and the second conductive plates form capacitors, the second conductive plates being arranged for coupling to second communication circuitry;
an attachment material selectively placed between the first die and a second IC die such that air gaps are formed between adjacent ones of the capacitors.

### Claim 13

A galvanic isolation device comprising:
an integrated circuit (IC) die having a top surface, an opposite bottom surface, and a side surface therebetween;
a first communication circuit formed in a circuit layer of the IC die;
a first conductive plate formed on the IC die proximate the top surface, the first conductive plate being coupled to the first communication circuit;
a dielectric isolation layer positioned on top of a portion of the top surface of the IC die, such that the dielectric isolation layer completely covers the first conductive plate and also covers an end surface of the IC die; and
a second conductive plate juxtaposed with the first conductive plate but separated from the first conductive plate by the dielectric isolation layer, such that the first conductive plate and the second conductive plate form a capacitor, the second conductive plate being arranged for coupling to a second communication circuit.

### Claim 14

A galvanic isolation device comprising:
an integrated circuit (IC) die having a top surface, an opposite bottom surface, and a side surface therebetween;
a first communication circuit formed in a circuit layer of the IC die;
a first conductive plate formed on the IC die proximate the top surface, the first conductive plate being coupled to the first communication circuit;
a dielectric isolation layer positioned on top of a portion of the top surface of the IC die, such that the dielectric isolation layer completely covers the first conductive plate and extends beyond a portion of the side surface of the IC die; and
a second conductive plate juxtaposed with the first conductive plate but separated from the first conductive plate by the dielectric isolation layer, such that the first conductive plate and the second conductive plate form a capacitor, the second conductive plate being arranged for coupling to a second communication circuit.

### Claim 15 (depends on 14)

The device of claim 14, wherein the IC die is a first IC die, and the device further comprises:
a second IC die;
the second communication circuit being formed in a circuit layer of the second IC die; and
the second conductive plate being a metallic plate formed in a metal interconnect layer of the second IC die.