# US 10,121,846 B1 · Resistor structure with high resistance based on very thin semiconductor layer > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,846 B1 - Document ID: US10121846B1 - Status: Granted - Kind: B1 - Application number: 15/620,923 - Filed: 2017-06-13 - Granted: 2018-11-06 - Earliest claimed: 2017-06-13 - Assignees: Globalfoundries Inc. - Applicants: GLOBALFOUNDRIES Inc. - Inventors: Alban Zaka; Ignasi Cortes Mayol; Tom Herrmann; El Mehdi Bazizi; John Morgan - Web page: https://patentgrep.com/patent/US10121846B1 ## CPC - H10D 1/47: Resistors having no potential barriers - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors} - H10D 84/817: {Combinations of field-effect devices and resistors only} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract The present disclosure provides resistor structures in sophisticated integrated circuits on the basis of an SOI architecture, wherein a very thin semiconductor layer, typically used for forming fully depleted SOI transistors, may be used as a resistor body. In this manner, significantly higher sheet resistance values may be achieved, thereby providing the potential for implementing high ohmic resistors into sophisticated integrated circuits. ## Claims ### Claim 1 An on-chip resistor structure, comprising a resistor body comprising a semiconductor layer having a thickness of approximately 15 nm or less, said semiconductor layer being formed on a buried insulating layer; at least one semiconductor region formed on said resistor body; and a first contact region and a second contact region positioned adjacent to and in electrical contact with said resistor body and being formed at least partially of a semiconductor material, said resistor body being laterally interposed between said first and second contact regions. ### Claim 2 (depends on 1) The on-chip resistor structure of claim 1, wherein a net dopant concentration of said at least one semiconductor region is higher than a net dopant concentration of said semiconductor layer. ### Claim 3 (depends on 1) The on-chip resistor structure of claim 1, wherein said at least one semiconductor region is one of two or more isolated semiconductor regions formed on said resistor body. ### Claim 4 (depends on 1) The on-chip resistor structure of claim 1, wherein said at least one semiconductor region is doped to have a conductivity type that is the same as a conductivity type of said semiconductor layer. ### Claim 5 (depends on 1) The on-chip resistor structure of claim 1, wherein said at least one semiconductor region is a raised semiconductor region. ### Claim 6 (depends on 1) The on-chip resistor structure of claim 1, wherein said semiconductor layer and said first and second contact regions are doped so as to have a same conductivity type. ### Claim 7 (depends on 6) The on-chip resistor structure of claim 6, wherein a net dopant concentration of said first and second contact regions is higher than a net dopant concentration of said semiconductor layer. ### Claim 8 (depends on 7) The on-chip resistor structure of claim 7, wherein said net dopant concentration of said semiconductor layer is less than 5×1018 cm−3. ### Claim 9 (depends on 7) The on-chip resistor structure of claim 7, wherein said net dopant concentration of said semiconductor layer is less than 5×1017 cm−3. ### Claim 10 (depends on 1) The on-chip resistor structure of claim 1, further comprising a back electrode structure formed below said semiconductor layer and comprising a portion of said buried insulating layer. ### Claim 11 (depends on 10) The on-chip resistor structure of claim 10, wherein said back electrode structure comprises a ferroelectric material. ### Claim 12 (depends on 10) The on-chip resistor structure of claim 10, wherein said back electrode structure comprises a semiconductor substrate material formed below said buried insulating layer. ### Claim 13 The on-chip resistor structure 1, further comprising one or more front electrode structures formed on portions of said semiconductor layer. ### Claim 14 (depends on 13) The on-chip resistor structure of claim 13, wherein said one or more front electrode structures comprise a ferroelectric material. ### Claim 15 A semiconductor device, comprising: a fully depleted field effect transistor formed in and on a first portion of a semiconductor layer formed on a buried insulating layer, said fully depleted field effect transistor comprising raised drain and source regions; and a resistor structure comprising a resistor body formed on a second portion of said semiconductor layer, said resistor structure comprising raised contact regions, wherein a configuration of said raised drain and source regions and a configuration of said contact regions are equivalent. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein said semiconductor layer has a thickness of 15 nm or less. ### Claim 17 An on-chip resistor structure, comprising a resistor body comprising a semiconductor layer having a thickness of approximately 15 nm or less, said semiconductor layer being formed on a buried insulating layer; a first contact region and a second contact region positioned adjacent to and in electrical contact with said resistor body and being formed at least partially of a semiconductor material, said resistor body being laterally interposed between said first and second contact regions; and a back electrode structure formed below said semiconductor layer, said back electrode structure comprising a portion of said buried insulating layer. ### Claim 18 (depends on 17) The on-chip resistor structure of claim 17, wherein said back electrode structure comprises a semiconductor substrate material formed below said buried insulating layer. ### Claim 19 (depends on 17) The on-chip resistor structure of claim 17, wherein said back electrode structure comprises a ferroelectric material.