# US 10,121,841 B2 · Display device, method of manufacturing the same, and electronic apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,841 B2 - Document ID: US10121841B2 - Status: Granted - Kind: B2 - Application number: 15/965,153 - Filed: 2018-04-27 - Published: 2018-09-13 - Granted: 2018-11-06 - Earliest claimed: 2013-09-12 - Assignees: Sony Corporation - Applicants: Sony Corporation - Inventors: Seiichiro Jinta - Web page: https://patentgrep.com/patent/US10121841B2 ## CPC - H10K 59/1213: {the pixel elements being TFTs} - G09G 3/2003: {Display of colours (specific for liquid crystal displays G09G3/3607)} - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - H10D 30/6731: {Top-gate only TFTs} - H10D 30/6732: {Bottom-gate only TFTs} - H10D 30/6734: {having gate electrodes arranged on both top and bottom sides of the channel, e.g. dual-gate TFTs} - H10D 30/6745: {Polycrystalline or microcrystalline silicon} - H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)} - H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)} - H10D 86/021: {of multiple TFTs} - H10D 86/0221: {comprising manufacture, treatment or patterning of TFT semiconductor bodies} - H10D 86/0227: {using structural arrangements to control crystal growth, e.g. placement of grain filters} - H10D 86/421: {having a particular composition, shape or crystalline structure of the active layer} - H10D 86/425: {having different crystal properties in different TFTs or within an individual TFT} - H10D 86/431: {having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs} - H10D 86/471: {having different architectures, e.g. having both top-gate and bottom-gate TFTs} - H10D 86/60: wherein the TFTs are in active matrices - H10K 50/13: comprising stacked EL layers within one EL unit - H10K 59/131: Interconnections, e.g. wiring lines or terminals - H10K 59/351: {comprising more than three subpixels, e.g. red-green-blue-white [RGBW]} - G09G 2230/00: Details of flat display driving waveforms - G09G 2300/0426: Layout of electrodes and connections - G09G 2300/0452: Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components - G09G 2300/0809: Several active elements per pixel in active matrix panels - G09G 2300/0842: forming a memory circuit, e.g. a dynamic memory with one capacitor - G09G 2310/08: Details of timing specific for flat panels, other than clock recovery - G09G 2320/02: Improving the quality of display appearance - H10K 59/1201: {Manufacture or treatment} - H10K 59/353: {characterised by the geometrical arrangement of the RGB subpixels} - H10K 59/38: comprising colour filters or colour changing media [CCM] - H10K 2102/3026: {Top emission} - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract There is provided a display device including: a light emitting element; and a drive transistor (DRTr) that includes a coupling section (W1) and a plurality of channel sections (CH) coupled in series through the coupling section (W1), wherein the drive transistor (DRTr) is configured to supply a drive current to the light emitting element. ## Claims ### Claim 1 A display device comprising: a plurality of pixels, at least one of the plurality of pixels includes a light emitting element; a drive transistor configured to supply a drive current to the light emitting element, the drive transistor including a first channel region, the first channel region including a first portion of a semiconductor layer, a first gate electrode, and an electrically-conductive layer, wherein the first channel region is formed on a first insulating layer, and the electrically-conductive layer is formed between the first insulating layer and a substrate; a write transistor configured to transfer a pixel voltage corresponding to a luminance intensity of the light emitting element, the write transistor including a second channel region, the second channel region including a second portion of the semiconductor layer, and a second gate electrode, wherein the second channel region is formed on the first insulating layer; a first metal wiring in contact with the semiconductor layer via a first contact region; and a second metal wiring in contact with the semiconductor layer via a second contact region, the first channel region being within a current path between the first contact region and the second contact region, wherein the write transistor does not include any electrically-conductive layers between the first insulating layer and the substrate, wherein a first part of the current path overlaps with the electrically-conductive layer, and wherein a second part of the current path does not overlap with the electrically-conductive layer. ### Claim 2 (depends on 1) The display device according to claim 1, wherein the at least one of the plurality of pixels further includes a capacitor having a first node and a second node, wherein the write transistor is connected between the first node of the capacitor and a data line, wherein the first gate electrode of the drive transistor is connected to the first node of the capacitor, and wherein the second node of the capacitor is connected to an anode electrode of the light emitting element. ### Claim 3 (depends on 1) The display device according to claim 1, wherein the electrically-conductive layer and the first gate electrode include a same material. ### Claim 4 (depends on 3) The display device according to claim 3, wherein the same material is molybdenum (Mo). ### Claim 5 (depends on 1) The display device according to claim 1, wherein only one insulating layer is disposed between the electrically-conductive layer and the first portion of the semiconductor layer of the drive transistor. ### Claim 6 (depends on 1) The display device according to claim 1, wherein the semiconductor layer within the current path includes a bent-shaped portion. ### Claim 7 (depends on 6) The display device according to claim 6, wherein the semiconductor layer within the current path includes a “U” shaped portion. ### Claim 8 (depends on 6) The display device according to claim 6, wherein the semiconductor layer within the current path includes a plurality of bent-shaped portions, and wherein at least one of the plurality of bent-shaped portions does not overlap with the first gate electrode or the electrically-conductive layer. ### Claim 9 (depends on 1) The display device according to claim 1, wherein the drive transistor further includes a second insulating layer, and wherein the first channel region is disposed between the first insulating layer and the second insulating layer. ### Claim 10 (depends on 1) The display device according to claim 1, wherein the write transistor further includes a second insulating layer, and wherein the second channel region is disposed between the first insulating layer and the second insulating layer. ### Claim 11 (depends on 1) The display device according to claim 1, wherein the drive transistor further includes a second insulating layer and a third insulating layer, wherein the first gate electrode is formed on the second insulating layer, and wherein the first gate electrode is disposed between the second insulating layer and the third insulating layer. ### Claim 12 (depends on 1) The display device according to claim 1, wherein the write transistor further includes a second insulating layer and a third insulating layer, wherein the second gate electrode is formed on the second insulating layer, and wherein the second gate electrode is disposed between the second insulating layer and the third insulating layer. ### Claim 13 (depends on 1) The display device according to claim 1, wherein, below the second channel region, the write transistor does not include any electrically-conductive layers between the first insulating layer and the substrate. ### Claim 14 (depends on 1) The display device according to claim 1, wherein a width of the electrically-conductive layer in a cross-section including the first contact region and the second contact region is smaller than a distance between the first contact region and the second contact region in the cross-section. ### Claim 15 (depends on 14) The display device according to claim 14, wherein the distance between the first contact region and the second contact region in the cross-section is larger than the width of the first gate electrode in the cross-section. ### Claim 16 A display device comprising: a plurality of pixels, at least one of the plurality of pixels includes a light emitting element; a drive transistor configured to supply a drive current to the light emitting element, the drive transistor including a first channel region, the first channel region a first portion of a semiconductor layer, a first gate electrode, and an electrically-conductive layer, wherein the first channel region is formed on a first insulating layer, and the electrically-conductive layer is formed between the first insulating layer and a substrate; a write transistor configured to transfer a pixel voltage corresponding to a luminance intensity of the light emitting element, the write transistor including a second channel region, the second channel region including a second portion of the semiconductor layer, and a second gate electrode, wherein the second channel region is formed on the first insulating layer; a first metal wiring in contact with the semiconductor layer via a first contact region; and a second metal wiring in contact with the semiconductor layer via a second contact region, the first channel region being within a current path between the first contact region and the second contact region, wherein the write transistor does not include any electrically-conductive layers between the first insulating layer and the substrate, wherein, in a plan view, the semiconductor layer within the current path has a recess portion above the electrically-conductive layer, and wherein, in the plan view, the first contact region overlaps with the electrically-conductive layer, and wherein, in the plan view, the second contact region overlaps with the electrically-conductive layer. ### Claim 17 (depends on 16) The display device according to claim 16, wherein the at least one of the plurality of pixels further includes a capacitor having a first node and a second node, wherein the write transistor is connected between the first node of the capacitor and a data line, wherein the first gate electrode of the drive transistor is connected to the first node of the capacitor, and wherein the second node of the capacitor is connected to an anode electrode of the light emitting element. ### Claim 18 (depends on 16) The display device according to claim 16, wherein the electrically-conductive layer and the first gate electrode include a same material. ### Claim 19 (depends on 18) The display device according to claim 18, wherein the same material is molybdenum (Mo). ### Claim 20 (depends on 16) The display device according to claim 16, wherein only one insulating layer is disposed between the electrically-conductive layer and the first channel region of the drive transistor. ### Claim 21 (depends on 16) The display device according to claim 16, wherein, in the plan view, at least a portion of the recess portion overlaps with the first gate electrode. ### Claim 22 (depends on 16) The display device according to claim 16, wherein, in the plan view, the semiconductor layer within the current path has a plurality of recess portions above the electrically-conductive layer, and wherein, in the plan view, at least one of the plurality of recess portions overlaps with the first gate electrode. ### Claim 23 (depends on 22) The display device according to claim 22, wherein, in the plan view, each of the recess portions overlaps with the first gate electrode. ### Claim 24 (depends on 22) The display device according to claim 22, wherein the plurality of recess portions includes a first recess portion and a second recess portion, wherein, in the plan view, the first recess portion is a recess in a first side of the semiconductor layer, and wherein, in the plan view, the second recess portion is a recess in a second side of the semiconductor layer that is opposite to the first side. ### Claim 25 (depends on 24) The display device according to claim 24, wherein the first recess portion and the second recess portion are arranged in a staggered layout. ### Claim 26 (depends on 16) The display device according to claim 16, wherein the drive transistor further includes a second insulating layer, and wherein the first channel region is disposed between the first insulating layer and the second insulating layer. ### Claim 27 (depends on 16) The display device according to claim 16, wherein the write transistor further includes a second insulating layer, and wherein the second channel region is disposed between the first insulating layer and the second insulating layer. ### Claim 28 (depends on 16) The display device according to claim 16, wherein the drive transistor further includes a second insulating layer and a third insulating layer, wherein the first gate electrode is formed on the second insulating layer, and wherein the first gate electrode is disposed between the second insulating layer and the third insulating layer. ### Claim 29 (depends on 16) The display device according to claim 16, wherein the write transistor further includes a second insulating layer and a third insulating layer, wherein the second gate electrode is formed on the second insulating layer, and wherein the second gate electrode is disposed between the second insulating layer and the third insulating layer. ### Claim 30 (depends on 16) The display device according to claim 16, wherein, below the second channel region, the write transistor does not include any electrically-conductive layers between the first insulating layer and the substrate, wherein the at least one of the plurality of pixels includes a third metal wiring in contact with the semiconductor layer via a third contact region and a fourth metal wiring in contact with the semiconductor layer via a fourth contact region, wherein the second channel region is within a second current path between the third contact region and the fourth contact region, and wherein the current path between the third contact region and the fourth contact region does not overlap with any electrically-conductive layers between the first insulating layer and the substrate.