# US 10,121,839 B2 · Display panel

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- Number: US 10,121,839 B2
- Document ID: US10121839B2
- Status: Granted
- Kind: B2
- Application number: 15/415,838
- Filed: 2017-01-25
- Published: 2017-05-11
- Granted: 2018-11-06
- Earliest claimed: 2014-02-11
- Assignees: Innolux Corporation
- Applicants: Innolux Corporation
- Inventors: Kuan-Feng Lee; Ming-Chang Lin; Tzu-Min Yan
- Web page: https://patentgrep.com/patent/US10121839B2

## CPC

- H10K 59/124: Insulating layers formed between TFT elements and OLED elements
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 86/451: {characterised by the compositions or shapes of the interlayer dielectrics}
- H10D 86/60: wherein the TFTs are in active matrices
- H10K 59/1213: {the pixel elements being TFTs}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 30/6755: {Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate}
- H10D 62/80: characterised by the materials
- H10D 62/875: {being semiconductor metal oxide, e.g. InGaZnO (Group II-VI materials H10D62/86; Group I-VI materials H10D62/871; Pb compounds or alloys H10D62/874)}
- H10D 86/423: {comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO}
- H10K 59/123: Connection of the pixel electrodes to the thin film transistors [TFT]
- H10K 2102/00: Constructional details relating to the organic devices covered by this subclass
- H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A display device including a TFT substrate and a display layer is provided. The TFT substrate includes a substrate, a gate layer, a semiconductor layer, a gate dielectric layer, a first electrode layer, a first passivation layer, a second passivation layer, and a second electrode layer. A via penetrates the first passivation layer and the second passivation layer to expose a portion of the first electrode layer, and the via has a sidewall. The second electrode layer is electrically connected to the first electrode layer through the via, the first passivation layer has a first edge on the sidewall of the via, the second passivation layer has a second edge on the sidewall of the via, and the first edge and the second edge are separated by a distance in the range of 500-2000 Å.

## Claims

### Claim 1

A display device, comprising:
a thin-film transistor (TFT) substrate, comprising:
a substrate;
a gate layer disposed on the substrate;
a semiconductor layer disposed on the substrate;
a gate dielectric layer disposed between the gate layer and the semiconductor layer;
a first electrode layer disposed on the semiconductor layer;
a first passivation layer disposed on the first electrode layer;
a second passivation layer disposed on the first passivation layer, wherein a via penetrates the first passivation layer and the second passivation layer to expose a portion of the first electrode layer, and the via has a sidewall; and
a second electrode layer disposed on the second passivation layer and electrically connected to the first electrode layer through the via, wherein the first passivation layer has a first edge on the sidewall of the via, the second passivation layer has a second edge on the sidewall of the via, and the first edge and the second edge are separated by a distance in the range of 500-2000 angstroms (Å); and
a display layer disposed on the TFT substrate.

### Claim 2 (depends on 1)

The display device according to claim 1, wherein the TFT substrate further has an insulating layer interposed between the first passivation layer and the second passivation layer.

### Claim 3 (depends on 1)

The display device according to claim 1, wherein on the sidewall of the via, the second passivation layer directly covers at least part of the first passivation layer.

### Claim 4 (depends on 1)

The display device according to claim 1, wherein the second passivation layer is composed of a first passivation film and a second passivation film, and the first passivation film is interposed between the first passivation layer and the second passivation film.

### Claim 5 (depends on 4)

The display device according to claim 4, wherein under the same etching condition, the etching rate of the first passivation film is smaller than the etching rate of the second passivation film.

### Claim 6 (depends on 1)

The display device according to claim 1, wherein the semiconductor layer is made of indium gallium zinc oxide (IGZO).

### Claim 7 (depends on 1)

The display device according to claim 1, wherein the first passivation layer is made of silicon oxide, and the second passivation layer is made of silicon nitride.

### Claim 8 (depends on 1)

The display device according to claim 1, wherein the display layer is a light-emitting layer.

### Claim 9

A display device, comprising:
a TFT substrate, comprising:
a substrate;
a gate layer disposed on the substrate;
a semiconductor layer disposed on the substrate;
a gate dielectric layer disposed between the gate layer and the semiconductor layer;
a first electrode layer disposed on the semiconductor layer;
a first passivation layer disposed on the first electrode layer, wherein the first passivation layer has a top surface;
a second passivation layer disposed on the first passivation layer, wherein a via penetrates the first passivation layer and the second passivation layer to expose a portion of the first electrode layer and to form a sidewall of the via, the first passivation layer has a first edge on the sidewall of the via, the second passivation layer has a second edge on the sidewall of the via, and the first edge and the second edge are separated by a distance in the range of 500-2000 angstroms (Å); and
a second electrode layer disposed on the second passivation layer and electrically connected to the first electrode layer through the via, wherein the second electrode layer covers and contacts at least part of the top surface of the first passivation layer, and the second electrode layer covers the sidewall of the via; and
a display layer disposed on the TFT substrate.

### Claim 10 (depends on 9)

The display device according to claim 9, wherein the TFT substrate further has an insulating layer interposed between the first passivation layer and the second passivation layer.

### Claim 11 (depends on 9)

The display device according to claim 9, wherein on the sidewall of the via, the second passivation layer directly covers at least partial of the first passivation layer.

### Claim 12 (depends on 11)

The display device according to claim 11, wherein the via has a center, and a distance between the second edge and the center of the via is greater than a distance between the first edge and the center of the via.

### Claim 13 (depends on 9)

The display device according to claim 9, wherein the second passivation layer is composed of a first passivation film and a second passivation film, and the first passivation film is interposed between the first passivation layer and the second passivation film.

### Claim 14 (depends on 13)

The display device according to claim 13, wherein under the same etching condition, the etching rate of the first passivation film is smaller than the etching rate of the second passivation film.

### Claim 15 (depends on 9)

The display device according to claim 9, wherein the semiconductor layer is made of indium gallium zinc oxide (IGZO).

### Claim 16 (depends on 9)

The display device according to claim 9, wherein the first passivation layer is made of silicon oxide, and the second passivation layer is made of silicon nitride.

### Claim 17 (depends on 9)

The display device according to claim 9, wherein the display layer is a light-emitting layer.