# US 10,121,827 B1 · Semiconductor structure and the method of making the same

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- Number: US 10,121,827 B1
- Document ID: US10121827B1
- Status: Granted
- Kind: B1
- Application number: 15/813,173
- Filed: 2017-11-15
- Granted: 2018-11-06
- Earliest claimed: 2017-10-18
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Chin-Fu Lin; Chung-Yi Chiu
- Web page: https://patentgrep.com/patent/US10121827B1

## CPC

- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10D 30/481: {FETs having two-dimensional material channels, e.g. transition metal dichalcogenide [TMD] FETs}
- H10D 30/6739: {Conductor-insulator-semiconductor electrodes}
- H10D 30/6741: {Group IV materials, e.g. germanium or silicon carbide (TFTs having oxide semiconductors H10D30/6755)}
- H10D 62/80: characterised by the materials
- H10D 62/882: {Graphene}
- H10D 62/883: {Transition metal dichalcogenides, e.g. MoSe2}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/20: Multistable switching devices, e.g. memristors
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

The present invention provides a semiconductor structure, the semiconductor structure includes a substrate defining a memory region and a transistor region, an insulating layer is disposed on the substrate, a 2D material layer disposed on the insulating layer, and disposed within the memory and the transistor region, parts of the 2D material layer within the transistor region is used as the channel region of a transistor structure, the transistor structure is disposed on the channel region. And a resistive random access memory (RRAM) located in the memory region, the RRAM includes a lower electrode layer, a resistance transition layer and an upper electrode layer being sequentially located on the 2D material layer and electrically connected to the channel region.

## Claims

### Claim 1

A semiconductor structure, comprising:
a substrate, a memory region and a transistor region are defined thereon;
an insulating layer disposed on the substrate;
a 2D material layer located on the insulating layer, and simultaneously located within the memory region and within the transistor region, wherein a portion of the 2D material layer within the transistor region is a channel region of a transistor, the transistor is disposed on the channel region within the transistor region; and
a resistive random access memory (RRAM) located within the memory region, the RRAM comprises a lower electrode layer, a resistive switching layer and an upper electrode layer sequentially located on a portion of the 2D material layer in the memory region, wherein the lower electrode layer contacts the 2D material layer directly, and the RRAM is electrically connected to the channel region.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the lower electrode layer is also located on a portion of the 2D material layer within the transistor region, and used as a source region and a drain of the transistor.

### Claim 3 (depends on 2)

The semiconductor structure of claim 2, further comprising a patterned dielectric layer disposed on the lower electrode layer within the transistor region.

### Claim 4 (depends on 3)

The semiconductor structure of claim 3, wherein the upper electrode layer is also located on the patterned dielectric layer within the transistor region, used as a gate of the transistor.

### Claim 5 (depends on 4)

The semiconductor structure of claim 4, wherein the transistor comprises the source region, the drain region, the patterned dielectric layer and the gate.

### Claim 6 (depends on 3)

The semiconductor structure of claim 3, wherein a portion of the patterned dielectric layer directly contacts the 2D material layer within the transistor region.

### Claim 7 (depends on 3)

The semiconductor structure of claim 3, wherein the material of the patterned dielectric layer is the same as the material of the resistance switching layer.

### Claim 8 (depends on 1)

The semiconductor structure of claim 1, wherein the upper electrode layer is located within the memory region and within the transistor region simultaneously, and a top surface of the upper electrode layer within the memory region is aligned with a top surface of the upper electrode layer within the transistor region.

### Claim 9 (depends on 8)

The semiconductor structure of claim 8, further comprising a conductive layer, disposed on the upper electrode layer within the transistor region and within the memory region, and a top surface of the conductive layer within the memory region is aligned with a top surface of the conductive layer within the transistor region.

### Claim 10 (depends on 1)

The semiconductor structure of claim 1, wherein the 2D material layer comprises graphene, phosphine or molybdenum disulfide (MoS2).

### Claim 11

A method for forming a semiconductor structure, comprising:
providing a substrate, a memory region and a transistor region are defined thereon;
forming an insulating layer on the substrate;
forming a 2D material layer located on the insulating layer and simultaneously located within the memory region and within the transistor region, wherein a portion of the 2D material layer within the transistor region is a channel region of a transistor, the transistor is disposed on the channel region within the transistor region; and
forming a resistive random access memory (RRAM) within the memory region, the RRAM comprises a lower electrode layer, a resistive switching layer and an upper electrode layer sequentially located on a portion of the 2D material layer in the memory region, wherein the lower electrode layer contacts the 2D material layer directly, and the RRAM is electrically connected to the channel region.

### Claim 12 (depends on 11)

The method of claim 11, wherein the lower electrode layer is also located on a portion of the 2D material layer within the transistor region, and used as a source region and a drain of the transistor.

### Claim 13 (depends on 12)

The method of claim 12, further comprising a patterned dielectric layer disposed on the lower electrode layer within the transistor region.

### Claim 14 (depends on 13)

The method of claim 13, wherein the upper electrode layer is also located on the patterned dielectric layer within the transistor region, used as a gate of the transistor.

### Claim 15 (depends on 14)

The method of claim 14, wherein the transistor comprises the source region, the drain region, the patterned dielectric layer and the gate.

### Claim 16 (depends on 13)

The method of claim 13, wherein a portion of the patterned dielectric layer directly contacts the 2D material layer within the transistor region.

### Claim 17 (depends on 13)

The method of claim 13, wherein the material of the patterned dielectric layer is the same as the material of the resistance switching layer.

### Claim 18 (depends on 11)

The method of claim 11, wherein the upper electrode layer is located within the memory region and within the transistor region simultaneously, and a top surface of the upper electrode layer within the memory region is aligned with a top surface of the upper electrode layer within the transistor region.

### Claim 19 (depends on 18)

The method of claim 18, further comprising a conductive layer, disposed on the upper electrode layer within the transistor region and within the memory region, and a top surface of the conductive layer within the memory region is aligned with a top surface of the conductive layer within the transistor region.

### Claim 20 (depends on 11)

The method of claim 11, wherein the 2D material layer comprises graphene, phosphine or molybdenum disulfide (MoS2).