# US 10,121,826 B1 · Semiconductor device and method of fabricating the same

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- Number: US 10,121,826 B1
- Document ID: US10121826B1
- Status: Granted
- Kind: B1
- Application number: 15/499,904
- Filed: 2017-04-28
- Published: 2018-11-01
- Granted: 2018-11-06
- Earliest claimed: 2017-04-28
- Assignees: Winbond Electronics Corp.
- Applicants: Winbond Electronics Corp.
- Inventors: Frederick Chen
- Web page: https://patentgrep.com/patent/US10121826B1

## CPC

- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1659: {Cell access}
- G11C 13/003: {Cell access}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10D 30/014: {of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron transistors [SET] or Coulomb blockade transistors}
- H10D 30/019: {of FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/501: {FETs having stacked nanowire, nanosheet or nanoribbon channels}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/121: {oriented parallel to substrates}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10N 50/01: Manufacture or treatment
- H10N 50/10: Magnetoresistive devices
- H10N 50/80: Constructional details
- H10N 70/00: Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching (integrated devices or assemblies of multiple devices H10N79/00)
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10W 20/43: Layouts of interconnections
- G11C 2213/71: Three dimensional array
- G11C 2213/75: Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
- G11C 2213/79: Array wherein the access device being a transistor
- H10D 30/43: having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6757: {characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715)}
- H10B: ELECTRONIC MEMORY DEVICES
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Provided are a semiconductor device including a plurality of transistors and a plurality of memory cells. Each of the transistors includes a gate structure and a source/drain region. The memory cells are respectively located over the gate structures. A lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors.

## Claims

### Claim 1

A semiconductor device comprising:
a plurality of transistors, each of the transistors comprising a gate structure and a source/drain region;
a plurality of memory cells respectively located over the gate structures, wherein a lower electrode of each of the memory cells and an upper electrode of an adjacent memory cell are electrically connected to the source/drain region between corresponding two transistors; and
a source line, coupled to one of the memory cells through a lower electrode of the one of the memory cells and a first plug, and coupled to a corresponding one of the transistors through the lower electrode of the one of the memory cells, the first plug and a second plug, wherein the lower electrode of the one of the memory cells is physically connected to and located between the first plug and the second plug.

### Claim 2 (depends on 1)

The semiconductor device as recited in claim 1, wherein the source/drain region between the corresponding two transistors is a source of one of the corresponding two transistors and a drain of the other of the corresponding two transistors.

### Claim 3 (depends on 1)

The semiconductor device as recited in claim 1, wherein the transistors comprise fin-type field effect transistors (FinFETs) or gate-all-around field effect transistors (GAA-FETs).

### Claim 4 (depends on 1)

The semiconductor device as recited in claim 1, wherein the memory cells comprise magnetic random access memories (MRAMs), resistive random access memories (RRAMs), or a combination thereof.

### Claim 5 (depends on 1)

The semiconductor device as recited in claim 1, wherein the memory cells are MRAMs, each of the MRAMs comprises a pinned layer, a free layer and a barrier layer therebetween, the pinned layer is connected to a corresponding lower electrode and the free layer is connected to a corresponding upper electrode.

### Claim 6 (depends on 1)

The semiconductor device as recited in claim 1, the memory cells are RRAMs, each of the RRAMs comprises a variable resistance layer between a corresponding lower electrode and a corresponding upper electrode.

### Claim 7 (depends on 1)

The semiconductor device as recited in claim 1, further comprising a bit line coupled to another of the transistors and corresponding another of the memory cells, wherein an extending direction of the bit line differs from an extending direction of the source line.

### Claim 8 (depends on 1)

The semiconductor device as recited in claim 1, wherein the upper electrode of each of the memory cells is electrically connected to the lower electrode of an adjacent memory cell by a plug, except for the memory cell whose upper electrode is connected to an overlying bit line.

### Claim 9

A semiconductor device comprising:
a plurality of semiconductor layers located on a substrate;
a plurality of isolation structures located over the substrate to isolate the semiconductor layers, wherein the semiconductor layers protrude from the isolation structures;
a plurality of gate structures respectively across at least portions of the semiconductor layers and portions of the isolation structures;
a plurality of memory cells respectively located over the gate structures between adjacent two semiconductor layers, wherein each of the memory cells comprises a lower electrode and an upper electrode, the lower electrode of each of the memory cells is electrically connected to the upper electrode of an adjacent memory cell; and
a source line, coupled to one of the memory cells through a lower electrode of the one of the memory cells and a first plug, and coupled to a corresponding one of the transistors through the lower electrode of the one of the memory cells, the first plug and a second plug, wherein the lower electrode of the one of the memory cells is physically connected to and located between the first plug and the second plug.

### Claim 10 (depends on 9)

The semiconductor device as recited in claim 9, wherein the lower electrode of each of the memory cells and the upper electrode of the adjacent memory cell are electrically connected to one semiconductor layer.

### Claim 11 (depends on 9)

The semiconductor device as recited in claim 9, wherein the memory cells comprise MRAMs, RRAMs, or a combination thereof.

### Claim 12 (depends on 9)

The semiconductor device as recited in claim 9, wherein the memory cells are MRAMs, each of the MRAMs comprises a pinned layer, a free layer and a barrier layer therebetween, the pinned layer is connected to a corresponding lower electrode and the free layer is connected to a corresponding upper electrode.

### Claim 13 (depends on 9)

The semiconductor device as recited in claim 9, the memory cells are RRAMs, each of the RRAMs comprises a variable resistance layer between a corresponding lower electrode and a corresponding upper electrode.

### Claim 14 (depends on 9)

The semiconductor device as recited in claim 9, further comprising a bit line coupled to another of the memory cells and corresponding another of the semiconductor layers, wherein an extending direction of the bit line differs from an extending direction of the source line.

### Claim 15 (depends on 9)

The semiconductor device as recited in claim 9, wherein the semiconductor layers comprise semiconductor fins extending along a first direction and the semiconductor fins and the isolation structures are arranged alternately along a second direction.

### Claim 16 (depends on 9)

The semiconductor device as recited in claim 9, wherein the semiconductor layers comprise nanowire stacks extending along a first direction and the nanowire stacks and the isolation structures are arranged alternately along a second direction.

### Claim 17 (depends on 16)

The semiconductor device as recited in claim 16, wherein the nanowire stacks are encapsulated by the gate structures extending along the second direction.

### Claim 18 (depends on 16)

The semiconductor device as recited in claim 16, wherein each of the nanowire stacks comprises a plurality of nanowires stacked along a direction perpendicular to a top surface of the substrate.

### Claim 19 (depends on 18)

The semiconductor device as recited in claim 18, wherein a linewidth of each of the nanowires is in a range of 5 nm to 50 nm.

### Claim 20 (depends on 18)

The semiconductor device as recited in claim 18, wherein a pitch of adjacent two nanowires is in a range of 5 nm to 20 nm.