# US 10,121,812 B2 · Stacked substrate structure with inter-tier interconnection

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- Number: US 10,121,812 B2
- Document ID: US10121812B2
- Status: Granted
- Kind: B2
- Application number: 15/365,064
- Filed: 2016-11-30
- Published: 2017-06-29
- Granted: 2018-11-06
- Earliest claimed: 2015-12-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Jeng-Shyan Lin; Dun-Nian Yaung; Jen-Cheng Liu; Hsun-Ying Huang; Wei-Chih Weng; Yu-Yang Shen
- Web page: https://patentgrep.com/patent/US10121812B2

## CPC

- H10F 39/809: {of hybrid image sensors}
- H10F 39/018: {of hybrid image sensors}
- H10F 39/807: {Pixel isolation structures}
- H10F 39/811: {Interconnections}
- H10P 54/00: Cutting or separating of wafers, substrates or parts of devices
- H10W 20/023: {the interconnections being through-semiconductor vias}
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/0253: {comprising forming the through-semiconductor vias after stacking of the chips, wafers or substrates}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/2125: {Top-view shapes}
- H10W 20/2134: {TSVs extending from the semiconductor wafer into back-end-of-line layers}
- H10W 20/435: {Cross-sectional shapes or dispositions of interconnections}
- H10W 72/00: Interconnections or connectors in packages
- H10W 90/00: Package configurations
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 80/312: {characterised by the direct bonding of electrically conductive pads}
- H10W 80/327: {characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers}
- H10W 90/792: {between multiple chips}
- H10F: INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to a method of forming a multi-dimensional integrated chip having tiers connected in a front-to-back configuration, and an associated apparatus. In some embodiments, the method is performed by forming one or more semiconductor devices within a first substrate, forming one or more image sensing elements within a second substrate, and bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure. An inter-tier interconnect structure, comprising a plurality of different segments, respectively having sidewalls with different sidewall angles, is formed to extend through the bonding structure and the second substrate. The inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate.

## Claims

### Claim 1

A method of forming a multi-dimensional integrated chip structure, comprising:
forming one or more semiconductor devices within a first substrate;
forming one or more image sensing elements within a second substrate;
bonding a first dielectric structure over the first substrate to a back-side of the second substrate by way of a bonding structure;
forming an inter-tier interconnect structure, comprising a plurality of different segments that respectively have sidewalls with different sidewall angles, which extends through the bonding structure and the second substrate, wherein the inter-tier interconnect structure is configured to electrically couple a first metal interconnect layer over the first substrate to a second metal interconnect layer over the second substrate; and
wherein the plurality of different segments comprise a first segment extending through the second substrate and a second segment surrounded by the bonding structure and contacting a bottom surface of the first segment at locations laterally separated from sidewalls of the first segment by non-zero distances.

### Claim 2 (depends on 1)

The method of claim 1, further comprising:
forming a first bonding etch stop layer (ESL) over a topmost conductive interconnect layer within the first dielectric structure over the first substrate;
forming a first dielectric bonding layer on the first bonding ESL; and
forming a second dielectric bonding layer along the back-side of the second substrate.

### Claim 3 (depends on 2)

The method of claim 2, further comprising:
reducing a thickness of the second substrate prior to forming the second dielectric bonding layer.

### Claim 4 (depends on 3)

The method of claim 3, wherein forming the inter-tier interconnect structure comprises:
bonding the first dielectric bonding layer to the second dielectric bonding layer;
performing a first etching process to form a first opening extending through the second substrate and having substantially vertical sidewalls;
performing a second etching process to form a second opening extending through the bonding structure and having a width that decreases as a distance from the second substrate increases;
filling the first opening and the second opening with a conductive material; and
forming one of more additional metal interconnect layers over the inter-tier interconnect structure and the second substrate.

### Claim 5 (depends on 4)

The method of claim 4, further comprising:
forming an isolation layer along sidewalls of the first opening prior to forming the second opening; and
forming a diffusion barrier layer lining sidewalls of the isolation layer and sidewalls and a lower surface of the second opening.

### Claim 6 (depends on 4)

The method of claim 4, further comprising:
forming a shallow trench isolation (STI) region within the second substrate; and
forming the first opening through the STI region, so that the first opening extends through the STI region at a location offset from outermost sidewalls of the STI region.

### Claim 7 (depends on 3)

The method of claim 3, wherein forming the inter-tier interconnect structure comprises:
performing a first etching process to form a first opening extending through the second substrate and having substantially vertical sidewalls;
filling the first opening with a first conductive material; and
performing a second etching process to form a second opening extending through the second dielectric bonding layer and a part of the first segment, wherein the second opening has a width that increases as a distance from the second substrate increases;
filling the second opening with a second conductive material;
performing a third etching process to form a third opening extending through the first dielectric bonding layer and the first bonding ESL, wherein the third opening has a width that increases as a distance from the first substrate increases;
filling the third opening with a third conductive material; and
bonding the first dielectric bonding layer to the second dielectric bonding layer after filling the third opening with the third conductive material; and
forming one of more additional metal interconnect layers over the inter-tier interconnect structure and the second substrate.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
forming a first bonding ESL over the first substrate;
forming the first dielectric bonding layer on the first bonding ESL;
forming a second bonding ESL along the back-side of the second substrate; and
forming the second dielectric bonding layer on the second bonding ESL.

### Claim 9 (depends on 8)

The method of claim 8, wherein forming the inter-tier interconnect structure comprises:
performing a first etching process to form a first opening extending through the second substrate and having substantially vertical sidewalls;
performing a second etching process to form a second opening extending through the bonding structure and having a width that decreases as a distance from the second substrate increases;
filling the first opening and the second opening with a first conductive material; and
performing a third etching process to form a third opening extending through the second dielectric bonding layer and the second bonding ESL, wherein the third opening has a width that increases as a distance from the second substrate increases;
filling the third opening with a second conductive material;
performing a fourth etching process to form a fourth opening extending through the first dielectric bonding layer and the first bonding ESL, wherein the fourth opening has a width that increases as a distance from the first substrate increases;
filling the fourth opening with a third conductive material;
bonding the first dielectric bonding layer to the second dielectric bonding layer after filling the fourth opening with the third conductive material; and
forming one of more additional metal interconnect layers over the inter-tier interconnect structure and the second substrate.

### Claim 10

A method of forming a multi-dimensional integrated chip structure, comprising:
forming one or more semiconductor devices within a first substrate;
forming a first plurality of metal interconnect layers within a first dielectric structure along a front-side of the first substrate;
forming a first dielectric bonding layer on a top surface of the first dielectric structure;
forming one or more image sensing elements within a second substrate;
forming one or more second metal interconnect layers within one or more dielectric layers arranged along a front-side of the second substrate;
forming a second dielectric bonding layer along a back-side of the second substrate;
bonding the first dielectric bonding layer to the second dielectric bonding layer;
forming an inter-tier interconnect structure configured to electrically couple the one or more semiconductor devices and the one or more image sensing elements; and
wherein the inter-tier interconnect structure comprises a first segment having substantially vertical sidewalls, a second segment having a width that increases as a distance from the second substrate increases, and a third segment separated from the first segment by the second segment and having a width that increases as a distance from the first substrate increases.

### Claim 11 (depends on 10)

The method of claim 10, further comprising:
forming one or more additional metal interconnect layers over the front-side of the second substrate.

### Claim 12

A multi-dimensional integrated chip structure, comprising:
a first plurality of metal interconnect layers arranged within a first dielectric structure over a first substrate;
a second plurality of metal interconnect layers arranged within a second dielectric structure over a second substrate;
a bonding structure arranged between the first dielectric structure and the second substrate;
an inter-tier interconnect structure extending between one of the first plurality of metal interconnect layers and one of the second plurality of metal interconnect layers and through the bonding structure and the second substrate, wherein the inter-tier interconnect structure comprises a plurality of different segments that respectively have sidewalls with different sidewall angles; and
wherein the plurality of different segments comprise a first region extending through the second substrate and a second region surrounded by the bonding structure, the second region contacting a bottom surface of the first region at locations laterally offset from sidewalls of the first region by non-zero distances.

### Claim 13 (depends on 12)

The integrated chip structure of claim 12, further comprising:
a diffusion barrier layer lining surfaces of the inter-tier interconnect structure, wherein the diffusion barrier layer has a horizontally extending surface extending between a first sidewall of the diffusion barrier layer lining the first region and a second sidewall of the diffusion barrier layer lining the second region.

### Claim 14 (depends on 13)

The integrated chip structure of claim 13, further comprising:
an isolation layer arranged along sidewalls of the first region and having a lower surface over the second region.

### Claim 15 (depends on 12)

The integrated chip structure of claim 12, wherein the bonding structure comprises:
a first dielectric bonding layer separated from the first substrate by a first dielectric etch stop layer; and
a second dielectric bonding layer arranged between the first dielectric bonding layer and the second substrate.

### Claim 16 (depends on 15)

The integrated chip structure of claim 15, wherein the first region has substantially vertical sidewalls and the second region has a width that increases as a distance from the second substrate increases; and
wherein the inter-tier interconnect structure further comprises a third region extending through the first dielectric bonding layer and having a width that decreases as a distance from the first substrate decreases.

### Claim 17 (depends on 16)

The integrated chip structure of claim 16, wherein the inter-tier interconnect structure further comprises a fourth region extending between the second substrate and the one of the second plurality of metal interconnect layers.

### Claim 18 (depends on 1)

The method of claim 1, wherein forming the inter-tier interconnect structure comprises:
performing a first etching process to form a first opening extending through the second substrate;
filling the first opening with a first conductive material;
performing a second etching process to form a second opening extending through the second dielectric bonding layer to the first conductive material;
filling the second opening with a second conductive material;
performing a third etching process to form a third opening extending through the first dielectric bonding layer;
filling the third opening with a third conductive material; and
bonding the first dielectric bonding layer to the second dielectric bonding layer after filling the third opening with the third conductive material.

### Claim 19 (depends on 1)

The method of claim 1, wherein a diffusion barrier layer lines surfaces of the inter-tier interconnect structure, the diffusion barrier layer having a horizontally extending surface extending between a first sidewall of the diffusion barrier layer lining the first segment and a second sidewall of the diffusion barrier layer lining the second segment.

### Claim 20 (depends on 1)

The method of claim 1,
wherein the first segment has substantially vertical sidewalls;
wherein the second segment has a width that increases as a distance from the second substrate increases; and
wherein the inter-tier interconnect structure further comprises a third segment having a width that increases as a distance from the first substrate increases.