# US 10,121,804 B2 · TFT substrate and manufacturing method thereof

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- Number: US 10,121,804 B2
- Document ID: US10121804B2
- Status: Granted
- Kind: B2
- Application number: 15/823,521
- Filed: 2017-11-27
- Published: 2018-03-22
- Granted: 2018-11-06
- Earliest claimed: 2016-06-02
- Assignees: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Applicants: Wuhan China Star Optoelectronics Technology Co., Ltd.
- Inventors: Liang Ma
- Web page: https://patentgrep.com/patent/US10121804B2

## CPC

- H10D 86/60: wherein the TFTs are in active matrices
- G02F 1/136204: {Arrangements to prevent high voltage or static electricity failures}
- G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)}
- H10D 86/0212: {comprising manufacture, treatment or coating of substrates}
- H10D 86/441: {Interconnections, e.g. scanning lines}
- H10D 89/911: {using passive elements as protective elements}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS

## Abstract

A TFT substrate and a manufacturing method thereof are provided. The TFT substrate includes a plurality of vias formed in a second insulation layer that is formed on a second metal layer that forms peripheral signal wiring traces of the TFT substrate so as to line up in an extension direction of each of the peripheral signal wiring traces and a third metal layer that is formed on the second insulation layer at a location corresponding to each of the peripheral signal wiring traces such that the third metal layer is connected, through the vias, with each of the peripheral signal wiring traces to thereby reduce the electrical resistance of each of the peripheral signal wiring traces and thus lowering down power consumption of control ICs and improving capability of the TFT substrate for resisting electrostatic discharge.

## Claims

### Claim 1

A manufacturing method of a thin-film transistor (TFT) substrate, comprising the following steps:
step 1, providing a backing plate, forming a first insulation layer on the backing plate, depositing and patterning a second metal layer on the first insulation layer, and forming a second insulation layer on the second metal layer,
wherein the second metal layer comprises a plurality of peripheral signal wiring traces;
step 2, forming, in the second insulation layer at locations corresponding to each of the peripheral signal wiring traces, a plurality of vias that is arranged in an extension direction of each of the peripheral signal wiring traces and extends through the second insulation layer;
step 3, depositing and patterning a third metal layer on the second insulation layer such that the third metal layer is formed at a location corresponding to each of the peripheral signal wiring traces and is electrically connected, through the plurality of vias, with each of the peripheral signal wiring traces; and
step 4, depositing a third insulation layer on the second insulation layer and the third metal layer to complete the manufacture of the TFT substrate;
wherein the plurality of peripheral signal wiring traces comprises high level direct-current (DC) signal lines, low level DC signal lines, and clock signal lines of a gate-driver-on-array (GOA) circuit and grounding lines of the TFT substrate.

### Claim 2 (depends on 1)

The manufacturing method of the TFT substrate as claimed in claim 1, wherein the first insulation layer comprises, stacked from bottom to top, a buffer layer, a gate insulation layer, and an interlayer dielectric layer.

### Claim 3 (depends on 1)

The manufacturing method of the TFT substrate as claimed in claim 1, wherein the second insulation layer comprises, stacked from bottom to top, a planarization layer and a top insulation layer.

### Claim 4 (depends on 1)

The manufacturing method of the TFT substrate as claimed in claim 1, wherein the first insulation layer comprises, stacked from bottom to top, a buffer layer, a gate insulation layer, and an interlayer dielectric layer and step 1 further comprises forming a first metal layer between the interlayer dielectric layer and the gate insulation layer.