# US 10,121,799 B2 · Elevationally-extending strings of memory cells individually comprising a programmable charge storage transistor and methods of processing silicon nitride-comprising materials

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- Number: US 10,121,799 B2
- Document ID: US10121799B2
- Status: Granted
- Kind: B2
- Application number: 15/851,532
- Filed: 2017-12-21
- Published: 2018-04-26
- Granted: 2018-11-06
- Earliest claimed: 2016-10-13
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Fei Wang; Tom J. John; Kunal Shrotri; Anish A. Khandekar; Aaron R. Wilson; John D. Hopkins; Derek F. Lundberg
- Web page: https://patentgrep.com/patent/US10121799B2

## CPC

- H10B 43/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10B 41/27: the channels comprising vertical portions, e.g. U-shaped channels
- H10D 30/683: {programmed by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling}
- H10P 50/283: {by chemical means}
- H10P 50/71: {using masks for conductive or resistive materials}
- H10P 50/73: {using masks for insulating materials}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A method comprises forming material to be etched over a substrate. An etch mask comprising a silicon nitride-comprising region is formed elevationally over the material. The etch mask comprises an elevationally-extending mask opening in the silicon nitride-comprising region that has a minimum horizontal open dimension that is greater in an elevationally-innermost portion of the region than in an elevationally-outermost portion of the region. The elevationally-outermost portion has a greater etch rate in at least one of HF and H3PO4 than does the elevationally-innermost portion. The etch mask is used as a mask while etching an elevationally-extending mask opening into the material. The silicon nitride-comprising region is exposed to at least one of HF and H3PO4 to increase the minimum horizontal open dimension in the elevationally-outermost portion to a greater degree than increase, if any, in the minimum horizontal open dimension in the elevationally-innermost portion. Other aspects and embodiments, including structure independent of method of manufacture, are disclosed.

## Claims

### Claim 1

An elevationally-extending string of memory cells individually comprising a programmable charge storage transistor, comprising:
vertically-alternating tiers of insulative material and control gate material;
a channel pillar extending elevationally through multiple of the vertically-alternating tiers and comprising a projecting portion extending elevationally outward of the elevationally-outermost tier of control gate material;
tunnel insulator, programmable charge storage material, and control gate blocking insulator between the channel pillar and the control gate material of individual of the tiers of the control gate material; and
silicon nitride-comprising material encircling at least some of the projecting portion of the channel pillar, the encircling silicon nitride-comprising material comprising an elevationally-outermost portion comprising boron, the encircling silicon nitride-comprising material comprising an elevationally-innermost portion having less boron content, if any, than the elevationally-outermost portion.

### Claim 2 (depends on 1)

The string of memory cells of claim 1 wherein said boron content is constant elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.

### Claim 3 (depends on 1)

The string of memory cells of claim 1 wherein boron is in the elevationally-innermost portion, said boron content being variable elevationally through each of the elevationally-outermost portion and the elevationally-innermost portion.

### Claim 4 (depends on 1)

The string of memory cells of claim 1 wherein the elevationally-outermost portion has 1 to 20 atomic percent boron.

### Claim 5 (depends on 1)

The string of memory cells of claim 1 wherein the elevationally-innermost portion has zero to 0.001 atomic percent boron.

### Claim 6 (depends on 1)

The string of memory cells of claim 1 wherein difference in said boron content is along a stepped gradient.

### Claim 7 (depends on 6)

The string of memory cells of claim 6 comprising three steps in the stepped gradient between an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.

### Claim 8 (depends on 1)

The string of memory cells of claim 1 wherein difference in said boron content is along a linear gradient.

### Claim 9 (depends on 8)

The string of memory cells of claim 8 wherein the linear gradient is straight.

### Claim 10 (depends on 9)

The string of memory cells of claim 9 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.

### Claim 11 (depends on 8)

The string of memory cells of claim 8 wherein the linear gradient is curved.

### Claim 12 (depends on 11)

The string of memory cells of claim 11 wherein the linear gradient is from an elevationally-outermost surface of the elevationally-outermost portion to an elevationally-innermost surface of the elevationally-innermost portion.