# US 10,121,790 B2 · Semiconductor device and method for fabricating the same

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- Number: US 10,121,790 B2
- Document ID: US10121790B2
- Status: Granted
- Kind: B2
- Application number: 15/802,472
- Filed: 2017-11-03
- Published: 2018-05-17
- Granted: 2018-11-06
- Earliest claimed: 2016-11-15
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: En-Chiuan Liou; Yu-Cheng Tung
- Web page: https://patentgrep.com/patent/US10121790B2

## CPC

- H10D 84/853: {comprising FinFETs}
- H10D 30/0241: {doping of vertical sidewalls, e.g. using tilted or multi-angled implants}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0172: {Manufacturing their gate conductors}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10P 14/6923: {the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG}
- H10P 14/69433: {the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz}
- H10P 32/1412: {through the applied layer}
- H10P 32/171: {being group IV material}
- H10D 84/0191: {Manufacturing their doped wells}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate;
forming a plurality of semiconductor fins on the semiconductor substrate;
forming a solid-state dopant source layer on the semiconductor fins;
forming an insulating buffer layer on the solid-state dopant source layer; and
forming a fin bump between the semiconductor fins, wherein the fin bump comprises a sidewall spacer, wherein the sidewall spacer does not cover a top surface of the fin bump.

### Claim 2 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, further comprising:
forming a dielectric layer on the insulating buffer layer and the fin bump;
recessing the dielectric layer, the insulating buffer layer and the solid-state dopant source layer to a level below a top surface of the semiconductor fins, exposing protruding portions of each of the plurality of semiconductor fins above sub-fin regions of each of the plurality of semiconductor fins; and
driving dopants from the solid-state dopant source layers into the sub-fin regions of each of the plurality of semiconductor fins.

### Claim 3 (depends on 2)

The method for fabricating a semiconductor device according to claim 2, further comprising:
forming a gate electrode traversing the protruding portions of each of the plurality of semiconductor fins;
forming source and drain regions in the protruding portions of each of the plurality of semiconductor fins, on either side of the gate electrode; and
cutting the gate electrode into gate segments.

### Claim 4 (depends on 3)

The method for fabricating a semiconductor device according to claim 3, wherein each of the gate segments has a gate edge that is partially overlapped with the fin bump when viewed from above.

### Claim 5 (depends on 4)

The method for fabricating a semiconductor device according to claim 4, wherein the gate edge does not completely overlap with the fin bump when viewed from above.

### Claim 6 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein the solid-state dopant source layer comprises a borosilicate glass (BSG) layer.

### Claim 7 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein the solid-state dopant source layer comprises a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.

### Claim 8 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein the insulating buffer layer comprises silicon nitride.

### Claim 9 (depends on 1)

The method for fabricating a semiconductor device according to claim 1, wherein the sidewall spacer comprises a residual portion of the solid-state dopant source layer and a residual portion of the insulating buffer layer.

### Claim 10

A semiconductor device, comprising:
a semiconductor substrate;
a plurality of semiconductor fins;
a solid-state dopant source layer on the semiconductor substrate,
an insulating buffer layer on the solid-state dopant source layer; and
a first fin bump, wherein the first fin bump comprises a first sidewall spacer, and wherein the first sidewall spacer does not cover a top surface of the fin bump.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the solid-state dopant source layer comprises a borosilicate glass (BSG) layer.

### Claim 12 (depends on 10)

The semiconductor device according to claim 10, wherein the solid-state dopant source layer comprises a phosphosilicate glass (PSG) layer or an arsenic silicate glass (AsSG) layer.

### Claim 13 (depends on 10)

The semiconductor device according to claim 10, wherein the insulating buffer layer comprises silicon nitride.

### Claim 14 (depends on 10)

The semiconductor device according to claim 10, wherein the first sidewall spacer comprises a residual portion of the solid-state dopant source layer and a residual portion of the insulating buffer layer.

### Claim 15 (depends on 10)

The semiconductor device according to claim 10 further comprises a recessed region in the semiconductor substrate and next to the first fin bump.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the recessed region is filled with a dielectric layer.

### Claim 17 (depends on 16)

The semiconductor device according to claim 16 further comprises a gate segment on the dielectric layer and a gate edge of the gate segment that is partially overlapped with the first fin bump.

### Claim 18 (depends on 10)

The semiconductor device according to claim 10, wherein the first sidewall spacer has a top surface that is higher than the top surface of the first fin bump.

### Claim 19 (depends on 10)

The semiconductor device according to claim 10 further comprises a second fin bump, wherein the second fin bump comprises a second sidewall spacer that has different structure from the first sidewall spacer.