# US 10,121,789 B2 · Self-aligned source/drain contacts

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- Number: US 10,121,789 B2
- Document ID: US10121789B2
- Status: Granted
- Kind: B2
- Application number: 15/396,924
- Filed: 2017-01-03
- Published: 2017-04-27
- Granted: 2018-11-06
- Earliest claimed: 2015-06-03
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Praneet Adusumilli; Emre Alptekin; Kangguo Cheng; Balasubramanian Pranatharthiharan; Shom S. Ponoth
- Web page: https://patentgrep.com/patent/US10121789B2

## CPC

- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0223: {having source and drain regions or source and drain extensions self-aligned to sides of the gate}
- H10D 30/0275: {forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions}
- H10D 30/0277: {forming conductor-insulator-semiconductor or Schottky barrier source or drain regions}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/165: {Tunnel injectors}
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/259: {Source or drain electrodes being self-aligned with the gate electrode and having bottom surfaces higher than the interface between the channel and the gate dielectric}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/42: using a gas or vapour
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor substrate includes lower source/drain (S/D) regions. A replacement metal gate (RMG) structure is arranged upon the semiconductor substrate between the lower S/D regions. Raised S/D regions are arranged upon the lower S/D regions adjacent to the RMG structure, respectively. The raised S/D regions may be recessed to form contact trenches. First self-aligned contacts are located upon the raised S/D regions within a first active area and second self-aligned contacts are located upon the recessed raised S/D regions in the second active area. The first and second self-aligned contacts allows for independent reduction of source drain contact resistances. The first self-aligned contacts may be MIS contacts or metal silicide contacts and the second self-aligned contacts may be metal-silicide contacts.

## Claims

### Claim 1

A semiconductor structure fabrication method comprising:
forming first lower source and drain (S&D) regions within or upon a first active area of a semiconductor substrate;
forming second lower S&D regions within or upon a second active area of the semiconductor substrate;
forming a first replacement metal gate (RMG) structure upon the semiconductor substrate between the first lower source region and the first lower drain region;
forming a second RMG structure upon the semiconductor substrate between the second lower source region and the second lower drain region;
forming a first raised source region upon the first lower source region adjacent to the first RMG structure and forming a first raised drain region upon the first lower drain region adjacent to the first RMG structure;
forming a second raised source region upon the second lower source region adjacent to the second RMG structure and forming a second raised drain region upon the second lower drain region adjacent to the second RMG structure;
recessing the first raised source region and recessing the first raised drain region forming first area contact trenches;
capping the first area contact trenches;
recessing the second raised source region and recessing the second raised drain region forming second area contact trenches;
forming second self-aligned contacts upon the second area contact trenches;
capping the second self-aligned contacts;
exposing the first area contract trenches;
forming first self-aligned contacts upon the exposed first area contact trenches.

### Claim 2 (depends on 1)

The semiconductor structure fabrication method of claim 1, wherein the first self-aligned contacts are metal-silicide contacts and wherein the second self-aligned contacts are metal-silicide contacts.

### Claim 3 (depends on 1)

The semiconductor structure fabrication method of claim 1, wherein recessing the first raised source region and recessing the first raised drain region is a self-aligned recess to the first active area of the semiconductor substrate and is selective to one or more materials of the second active area of the semiconductor substrate.

### Claim 4 (depends on 1)

The semiconductor structure fabrication method of claim 1, wherein recessing the second raised source region and recessing the second raised drain region is a self-aligned recess to the second active area of the semiconductor substrate and is selective to one or more materials of the first active area of the semiconductor substrate.

### Claim 5 (depends on 1)

The semiconductor structure fabrication method of claim 1, wherein the first active area of the semiconductor substrate is an n-type field-effect-transistor (nFET) area and wherein the second active area of the semiconductor substrate is a p-type field-effect-transistor (pFET) area.

### Claim 6 (depends on 1)

The semiconductor structure fabrication method of claim 1, wherein the first active area of the semiconductor substrate is a p-type field-effect-transistor (pFET) area and wherein the second active area of the semiconductor substrate is an n-type field-effect-transistor (nFET) area.

### Claim 7 (depends on 1)

The semiconductor structure fabrication method of claim 1, wherein the first area contact trenches comprise vertical sidewalls or comprise v-shaped sidewalls.

### Claim 8 (depends on 1)

The semiconductor structure fabrication method of claim 1, wherein the second area contact trenches comprise vertical sidewalls or comprise v-shaped sidewalls.

### Claim 9

A semiconductor structure comprising:
a semiconductor substrate comprising first lower source and drain (S&D) regions in a first active area of the semiconductor structure and second lower source and drain (S&D) regions in a second active area of the semiconductor structure;
a first replacement metal gate (RMG) structure upon the semiconductor substrate between the first lower source region and the first lower drain region;
a second RMG structure upon the semiconductor substrate between the second lower source region and the second lower drain region;
a first raised source region upon the first lower source region adjacent to the first RMG structure and a first raised drain region upon the first lower drain region adjacent to the first RMG structure;
a second raised source region upon the second lower source region adjacent to the second RMG structure and a second raised drain region upon the second lower drain region adjacent to the second RMG structure;
first active area contact trenches within the first raised S&D regions;
second active area contact trenches within the second raised S&D regions;
self-aligned n-type metal silicide contacts within the first area contact trenches; and
self-aligned p-type metal-silicide contacts within the second area contact trenches.

### Claim 10 (depends on 9)

The semiconductor structure of claim 9, wherein the first active area is an n-type field-effect-transistor (nFET) area and wherein the second active area is a p-type field-effect-transistor (pFET) area.

### Claim 11 (depends on 9)

The semiconductor structure claim 9, wherein the first active area is a p-type field-effect-transistor (pFET) area and wherein the second active area is an n-type field-effect-transistor (nFET) area.

### Claim 12 (depends on 9)

The semiconductor structure of claim 9, wherein the first active area contact trenches comprise vertical sidewalls.

### Claim 13 (depends on 9)

The semiconductor structure of claim 9, wherein the first active area contact trenches comprise v-shaped sidewalls.

### Claim 14 (depends on 9)

The semiconductor structure of claim 9, wherein the second active area contact trenches comprise vertical sidewalls.

### Claim 15 (depends on 9)

The semiconductor structure of claim 9, wherein the second active area contact trenches comprise v-shaped sidewalls.