# US 10,121,787 B2 · Methods for fabricating Fin field effect transistors

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- Number: US 10,121,787 B2
- Document ID: US10121787B2
- Status: Granted
- Kind: B2
- Application number: 15/706,760
- Filed: 2017-09-17
- Published: 2018-01-25
- Granted: 2018-11-06
- Earliest claimed: 2016-02-05
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Che-Cheng Chang; Chih-Han Lin; Horng-Huei Tseng
- Web page: https://patentgrep.com/patent/US10121787B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/8316: {the IGFETs characterised by having gate sidewall spacers specially adapted for integration}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Method for fabricating Fin field effect transistors (FinFETs) are disclosed. One of the methods includes the following steps. A first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin are formed. A first dummy gate, a second dummy gate and an opening between the first and second dummy gates are formed over the insulator, wherein the first dummy gate and the second dummy gate cross over portions of the first semiconductor fin and the second semiconductor fin respectively. A dielectric layer is formed in the opening, wherein the dielectric layer comprises an air gap therein. The first dummy gate and the second dummy gate are replaced with a first gate and a second gate, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein.

## Claims

### Claim 1

A method for fabricating a fin field effect transistor (FinFET), comprising:
forming a first semiconductor fin, a second semiconductor fin and an insulator between the first and second semiconductor fins;
forming a dummy gate strip over the insulator to cross over portions of the first semiconductor fin and the second semiconductor fin;
forming an opening in the dummy gate strip; and
forming a dielectric layer in the opening, wherein an air gap is formed in the dielectric layer when the dielectric layer is formed in the opening.

### Claim 2 (depends on 1)

The method of claim 1, wherein the insulator is formed between lower portions of the first and second semiconductor fins, and the dummy gate strip surrounds upper portions of the first semiconductor fin and the second semiconductor fin respectively.

### Claim 3 (depends on 1)

The method of claim 1, wherein a bottom surface of the air gap is higher than a bottom surface of the dummy gate strip.

### Claim 4 (depends on 1)

The method of claim 1, wherein a top critical dimension of the opening is smaller than or substantially equal to a bottom critical dimension of the dielectric layer.

### Claim 5 (depends on 1)

The method of claim 1, wherein the dielectric layer is further formed over the first and second semiconductor fins.

### Claim 6

A method for fabricating a fin field effect transistor (FinFET), comprising:
forming a first semiconductor fin, a second semiconductor fin and an insulator between the first semiconductor fin and the second semiconductor fin;
forming a dummy gate strip over the insulator to cross over portions of the first semiconductor fin and the second semiconductor fin;
cutting the dummy gate strip to form a first dummy gate, a second dummy gate and an opening, wherein an end of the first dummy gate is adjacent to an end of the second dummy gate, and the opening is an end-to-end opening between the end of the first dummy gate and the end of the second dummy gate;
filling a dielectric layer in the opening, wherein an air gap is formed in the dielectric layer simultaneously during filling the dielectric layer in the opening;
removing the first dummy gate and a second dummy gate; and
forming a first gate and a second gate to cross over the first semiconductor fin and the second semiconductor fin respectively, wherein the first gate and the second gate are electrically insulated by the dielectric layer comprising the air gap therein.

### Claim 7 (depends on 6)

The method of claim 6, wherein the opening includes a top portion and a bottom portion, the top portion has straight sidewalls, and the bottom portion has inclined sidewalls.

### Claim 8 (depends on 6)

The method of claim 6, wherein a bottom surface of the air gap is higher than a bottom surface of at least one of the first gate and the second gate.

### Claim 9

A method for fabricating a fin field effect transistor (FinFET), comprising:
patterning a substrate to form a first semiconductor fin, a second semiconductor fin and a trench between the first semiconductor fin and the second semiconductor fin;
forming an insulator in the trench;
forming a dummy gate strip over the insulator to cross over portions of the first semiconductor fin and the second semiconductor fin;
forming an opening in the dummy gate strip, so as to separate the dummy gate strip into a first dummy gate and a second dummy gate on the first semiconductor fin and the second semiconductor fin respectively;
forming a dielectric material to fill in the opening and cover the first dummy gate and the second dummy gate, wherein the air gap is formed simultaneously with the dielectric material;
removing a portion of the dielectric material to form a first dielectric layer, wherein the air gap is retained in the first dielectric layer; and
replacing the first dummy gate and the second dummy gate with a first gate and a second gate respectively, wherein the first gate and the second gate are electrically insulated by the first dielectric layer comprising the air gap therein, and a bottom of the air gap is higher than a bottom of at least one of the first gate and the second gate.

### Claim 10 (depends on 9)

The method of claim 9, wherein the air gap is enclosed by the first dielectric layer.

### Claim 11 (depends on 9)

The method of claim 9, wherein the opening is formed with a top critical dimension smaller than or substantially equal to a bottom critical dimension thereof.

### Claim 12 (depends on 9)

The method of claim 9, wherein the opening includes a top portion and a bottom portion, the top portion has straight sidewalls, and the bottom portion has inclined sidewalls.

### Claim 13 (depends on 9)

The method of claim 9, wherein a top surface of the first dielectric layer is substantially coplanar with top surfaces of the first and second dummy gates.

### Claim 14 (depends on 9)

The method of claim 9 further comprising forming a second dielectric layer on the first and second semiconductor fins and sidewalls of the first dielectric layer after removing the first dummy gate and the second dummy gate.

### Claim 15 (depends on 14)

The method of claim 14 further comprising forming a third dielectric layer disposed between the first semiconductor fin and the second dielectric layer and between the second semiconductor fin and the second dielectric layer.

### Claim 16 (depends on 1)

The method of claim 1, wherein the air gap is enclosed by the dielectric layer.

### Claim 17 (depends on 1)

The method of claim 1, wherein the opening divides the dummy gate strip into two parts.

### Claim 18 (depends on 6)

The method of claim 6, wherein a top critical dimension of the opening is smaller than or substantially equal to a bottom critical dimension of the opening.

### Claim 19 (depends on 6)

The method of claim 6, wherein the air gap is enclosed by the dielectric layer.

### Claim 20 (depends on 7)

The method of claim 7, wherein the straight sidewalls are substantially perpendicular to an extended direction of the dummy gate strip and an extended direction of the first semiconductor fin.