# US 10,121,786 B2 · FinFET with U-shaped channel and S/D epitaxial cladding extending under gate spacers

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- Number: US 10,121,786 B2
- Document ID: US10121786B2
- Status: Granted
- Kind: B2
- Application number: 15/464,213
- Filed: 2017-03-20
- Published: 2017-07-06
- Granted: 2018-11-06
- Earliest claimed: 2015-06-30
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Takashi Ando; Robert H. Dennard; Isaac Lauer; Ramachandran Muralidhar; Ghavam G. Shahidi
- Web page: https://patentgrep.com/patent/US10121786B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/0245: {by further thinning the channel after patterning the channel, e.g. using sacrificial oxidation on fins}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/292: {Non-planar channels of IGFETs (resulting from the gate electrode dispositions, e.g. within trenches H10D64/512)}
- H10D 64/01316: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. Ta, W, Mo or Al}
- H10D 64/01318: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/665: {the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum (having lateral variation H10D64/671)}
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 84/0147: {Manufacturing their gate sidewall spacers}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3438: {Doping during depositing}
- H10P 14/69392: {the material containing hafnium, e.g. HfO2}
- H10P 14/69396: {the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

In one aspect, a method of forming finFET devices is provided which includes patterning fins in a wafer; forming dummy gates over the fins; forming spacers on opposite sides of the dummy gates; depositing a gap fill oxide on the wafer, filling any gaps between the spacers; removing the dummy gates forming gate trenches; trimming the fins within the gate trenches such that a width of the fins within the gate trenches is less than the width of the fins under the spacers adjacent to the gate trenches, wherein u-shaped grooves are formed in sides of the fins within the gate trenches; and forming replacement gate stacks in the gate trenches, wherein portions of the fins adjacent to the replacement gate stacks serve as source and drain regions of the finFET devices.

## Claims

### Claim 1

A fin field-effect transistor (FinFET) device, comprising:
fins patterned in a wafer;
a gate stack between gate spacers and over portions of the fins that serve as channel regions of the finFET device, wherein portions of the fins adjacent to the gate stack serve as source and drain regions of the finFET device, wherein a width of the fins under the gate stack is less than the width of the fins adjacent to the gate stack, and wherein u-shaped grooves are provided in sides of the fins under the gate stack; and
a doped epitaxial cladding layer on the fins in the source and drain regions of the finFET device and under the gate spacers, wherein the doped epitaxial cladding layer extends at least up to, and abuts, the gate stack.

### Claim 2 (depends on 1)

The finFET device of claim 1, wherein the doped epitaxial cladding layer comprises epitaxial silicon, germanium, or silicon germanium, and wherein the doped epitaxial cladding layer is in-situ doped with an n-type or a p-type dopant.

### Claim 3 (depends on 1)

The finFET device of claim 1, wherein the doped epitaxial cladding layer has a thickness of less than or equal to about 3 nm.

### Claim 4 (depends on 1)

The finFET device of claim 1, wherein the width of the fins adjacent to the gate stack increases from a top to a bottom of each of the fins.

### Claim 5 (depends on 1)

The finFET device of claim 1, wherein the doped epitaxial cladding layer extends under the gate stack.