# US 10,121,785 B2 · Pitch scalable active area patterning structure and process for multi-channel fin FET technologies

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,785 B2
- Document ID: US10121785B2
- Status: Granted
- Kind: B2
- Application number: 15/397,123
- Filed: 2017-01-03
- Published: 2017-07-27
- Granted: 2018-11-06
- Earliest claimed: 2016-01-22
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Sivananda K. Kanakasabapathy; Fee Li Lie; Eric Miller; Stuart A. Sieg
- Web page: https://patentgrep.com/patent/US10121785B2

## CPC

- H10D 84/834: {comprising FinFETs}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/853: {comprising FinFETs}
- H10P 50/692: {characterised by their composition, e.g. multilayer masks or materials}
- H10P 50/695: {characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask}
- H10P 50/73: {using masks for insulating materials}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Provided herein is a multi-channel finFET having a plurality of fins prepared by a process. The process includes forming a series of mandrels on hard mask layer which overlays a semiconductor layer. The semiconductor layer has areas of a first semiconductor material and a second semiconductor material in contact with the hard mask layer. The process includes applying a first conformal coating on the hard mask layer and the series of mandrels, to form spacer layer sacrificial fins. The process includes removing the first conformal coating from horizontal surfaces while retaining the first conformal coating on sidewalls of the series of mandrels. The process includes removing the series of mandrels and etching into a material of the hard mask layer using the spacer layer sacrificial fins as a mask.

## Claims

### Claim 1

A multi-channel finFET comprising:
a hard mask layer;
a semiconductor layer having areas of a first semiconductor material and a second semiconductor material in contact with the hard mask layer, wherein the semiconductor layer having its longest dimension in an x-y direction;
a plurality of fins of desired dimension in the first semiconductor material and the second semiconductor material, wherein the plurality of fins have their longest dimension in a z-direction, wherein the z-direction is normal to the x-y plane;
a first conformal coating layer on the plurality of fins;
a second conformal coating layer on the first conformal coating layer;
a third conformal coating layer on the second conformal coating layer,
wherein the first conformal coating layer comprises a thickness of 5 to 20 nanometers,
wherein the second conformal coating layer comprises a thickness of 1 to 5 nanometers,
wherein the first conformal coating layer and the second conformal coating layer are different materials selected from silicon oxide, silicon nitride, SiBCN (silicon borocarbon nitride), and SiOCN (silicon oxycarbon nitride).