# US 10,121,784 B2 · Semiconductor apparatus > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,784 B2 - Document ID: US10121784B2 - Status: Granted - Kind: B2 - Application number: 15/044,875 - Filed: 2016-02-16 - Published: 2016-06-09 - Granted: 2018-11-06 - Earliest claimed: 2013-11-12 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Junichi Nita; Kazutaka Suzuki; Takahiro Korenari; Yoshimasa Uchinuma - Web page: https://patentgrep.com/patent/US10121784B2 ## CPC - H10D 84/83: of only insulated-gate FETs [IGFET] - H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence) - H10D 30/668: {having trench gate electrodes, e.g. UMOS transistors} - H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates} - H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes} - H10D 84/016: {the components including vertical IGFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/83125: {the IGFETs characterised by having shared source or drain regions} - H10D 84/839: {comprising VDMOS} - H10D 89/10: Integrated device layouts - H10W 20/0698: {Local interconnections} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10D 62/127: {of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs} - H10D 62/154: {Dispositions} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor apparatus includes a first area, a first transistor being formed in two or more divided areas of the first area, and a second area, a second transistor being formed in two or more divided areas of the second area. The number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and the gate pad of the first transistor and the gate pad of the second transistor are formed in the second area. ## Claims ### Claim 1 A semiconductor apparatus comprising: a first area, a first transistor being formed in two or more divided areas of the first area; and a second area, a second transistor being formed in two or more divided areas of the second area, wherein the number of areas of the second area is greater than the number of areas of the first area, the divided areas of the first area and the second area are alternately arranged, and a first source pad connected to a source of the first transistor is formed in the first area, and a second source pad connected to a source of the second transistor is formed in the second area. ### Claim 2 (depends on 1) The semiconductor apparatus according to claim 1, wherein a gate pad of the first transistor and a gate pad of the second transistor are formed in the second area, a gate line of the first transistor is formed continuously across the divided first area that is connected to the gate pad of the first transistor, and a gate line of the second transistor is formed continuously across the second area that is connected to the gate pad of the second transistor. ### Claim 3 (depends on 1) The semiconductor apparatus according to claim 1, wherein the first transistor and the second transistor are trench transistors, and a current flowing from the source of the first transistor is output from the source of the second transistor via a substrate area of the semiconductor apparatus. ### Claim 4 (depends on 1) The semiconductor apparatus according to claim 1, wherein a total area of the second area is larger than a total area of the first area, and the total number of the number of divisions of the first area and the number of divisions of the second area is five or greater. ### Claim 5 (depends on 1) The semiconductor apparatus according to claim 1, wherein a total area of the second source pad is larger than a total area of the first source pad; or the first source pad comprises a plurality of first source pads and the second source pad comprises a plurality of second source pads, and the number of the second source pads is greater than the number of the first source pads. ### Claim 6 (depends on 5) The semiconductor apparatus according to claim 5, wherein the first source pad and the second source pad have continuous shapes in each of the divided areas. ### Claim 7 (depends on 1) The semiconductor apparatus according to claim 1, wherein a gate pad of the first transistor and a gate pad of the second transistor are formed in the second area, and the gate pad of the first transistor and the gate pad of the second transistor are arranged along a contour of the semiconductor chip on which the first transistor and the second transistor are formed. ### Claim 8 (depends on 7) The semiconductor apparatus according to claim 7, wherein the second source pad comprises a plurality of second source pads, and the second area includes a plurality of source pad sequences in which the second source pads are continuously arranged, and the gate pad of the first transistor and the gate pad of the second transistor are disposed in the same source pad sequence among the plurality of source pad sequences. ### Claim 9 (depends on 7) The semiconductor apparatus according to claim 7, wherein the gate pad of the first transistor and the gate pad of the second transistor are arranged diagonally on the semiconductor chip. ### Claim 10 (depends on 7) The semiconductor apparatus according to claim 7, wherein the second source pad comprises a plurality of second source pads, and the second area includes a plurality of source pad sequences in which the second source pads are consecutively arranged, and the gate pad of the first transistor and the gate pad of the second transistor are disposed in different source pad sequences from each other among the plurality of source pad sequences. ### Claim 11 (depends on 1) The semiconductor apparatus according to claim 1, wherein a gate pad of the first transistor and a gate pad of the second transistor are formed in the second area, trench gate electrodes that are connected to the respective gate pads are formed in the first area and the second area, and the trench gate electrode formed in the first area and the trench gate electrode formed in the second area are formed to extend in directions that are orthogonal to each other. ### Claim 12 (depends on 1) The semiconductor apparatus according to claim 1, wherein a gate pad of the first transistor and a gate pad of the second transistor are formed in the second area, and wherein the semiconductor apparatus further comprises: a gate line of the first transistor, the gate line comprising a polygonal shape where the gate pad is formed. ### Claim 13 (depends on 1) The semiconductor apparatus according to claim 1, wherein a gate pad of the first transistor and a gate pad of the second transistor are formed in the second area, and wherein the semiconductor apparatus further comprises: a back-metal layer on a second plane, the second plane being opposed to a first plane where the gate pad is provided among planes of the semiconductor chip on which the first transistor and the second transistor are formed. ### Claim 14 (depends on 1) The semiconductor apparatus according to claim 1, further comprising: a semiconductor substrate of a first conductivity-type; a metal layer formed on a back surface of the semiconductor substrate; an epitaxial layer formed on a front surface of the semiconductor substrate; a second conductivity-type diffusion layer formed on the epitaxial layer; and a first conductivity-type diffusion layer formed on the second conductivity-type diffusion layer, wherein the first and second transistors comprise vertical transistors which are formed in a trench formed in the first conductivity-type diffusion layer, the second conductivity-type diffusion layer and the epitaxial layer. ### Claim 15 (depends on 1) The semiconductor apparatus according to claim 1, wherein a gate pad of the first transistor and a gate pad of the second transistor are formed in the second area, and wherein the first source pad comprises a plurality of first source pads, and the semiconductor apparatus further comprises: a first gate line of the first transistor, which is formed in the first area and surrounds the plurality of first source pads, and comprises: a pair of long sections; a pair of short sections which connect the ends of the pair of long sections; and an extended portion which extends from a long section of the plurality of long sections, into the second area and connects to the gate pad of the first transistor. ### Claim 16 A semiconductor apparatus comprising: a first area, a first transistor being formed in two or more divided areas of the first area; and a second area, a second transistor being formed in two or more divided areas of the second area, wherein the number of areas of the second area is greater than the number of areas of the first area, wherein the divided areas of the first area and the second area are alternately arranged, and wherein each of the first and second transistors comprise a trench transistor, and a current flowing from a source of the first transistor is output from a source of the second transistor via a substrate area of the semiconductor apparatus. ### Claim 17 A semiconductor apparatus comprising: a first area, a first transistor being formed in two or more divided areas of the first area; and a second area, a second transistor being formed in two or more divided areas of the second area, wherein the number of areas of the second area is greater than the number of areas of the first area, wherein the divided areas of the first area and the second area are alternately arranged, and wherein a total area of the second area is larger than a total area of the first area, and the total number of the number of divisions of the first area and the number of divisions of the second area is five or greater.