# US 10,121,783 B2 · Semiconductor integrated circuit and semiconductor module

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- Number: US 10,121,783 B2
- Document ID: US10121783B2
- Status: Granted
- Kind: B2
- Application number: 15/641,604
- Filed: 2017-07-05
- Published: 2018-03-01
- Granted: 2018-11-06
- Earliest claimed: 2016-08-29
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Hiroshi Kanno; Masaharu Yamaji; Akihiro Jonishi
- Web page: https://patentgrep.com/patent/US10121783B2

## CPC

- H10D 84/811: {Combinations of field-effect devices and one or more diodes, capacitors or resistors}
- H03K 17/6872: {using complementary field-effect transistors}
- H10D 30/65: Lateral DMOS [LDMOS] FETs
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 90/00: Package configurations
- H03K 2217/0063: High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
- H03K 2217/0072: Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
- H10D 84/0191: {Manufacturing their doped wells}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10W 72/07351: {characterised by changes in properties of the die-attach connectors during connecting}
- H10W 72/30: Die-attach connectors
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor integrated circuit includes a semiconductor substrate of a first conductivity type, a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate, a second well region of the first conductivity type formed in an upper portion of the first well region, an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate that is directly beneath the first well region, and a rear surface electrode layer formed on a bottom of the insulating layer.

## Claims

### Claim 1

A semiconductor module, comprising:
a semiconductor integrated circuit including:
a semiconductor substrate of a first conductivity type;
a first well region of a second conductivity type formed in an upper portion of the semiconductor substrate;
a second well region of the first conductivity type formed in an upper portion of the first well region;
an insulating layer formed separated from the first well region on a bottom portion of the semiconductor substrate directly beneath the first well region; and
a rear surface electrode layer formed below the insulating layer;
an insulated circuit board having formed on a surface thereof a conductive layer on which to mount the semiconductor integrated circuit;
a bonding layer that is interposed between the conductive layer and the rear surface electrode layer and bonds together the rear surface electrode layer and the conductive layer;
a first active element including a first main electrode region and a second main electrode region both of the first conductivity type and formed in an upper portion of the first well region;
a second active element including a third main electrode region and a fourth main electrode region both of the second conductivity type and formed in an upper portion of the second well region; and
a switching element that is mounted on the insulated circuit board and controlled by the first active element and the second active element.

### Claim 2 (depends on 1)

The semiconductor module according to claim 1, wherein the semiconductor integrated circuit and the switching element are mounted at a same height.

### Claim 3 (depends on 1)

The semiconductor module according to claim 1,
wherein a first voltage is applied to the first well region, and
wherein a second voltage that is different from the first voltage is applied to the second well region.

### Claim 4 (depends on 3)

The semiconductor module according to claim 3, wherein a distance between the first well region and the insulating layer is set such that, when the first voltage is applied to the first well region and the second voltage is applied to the second well region, a depletion layer that expands out from a p-n junction between the semiconductor substrate and the first well region is separated from the insulating layer.

### Claim 5 (depends on 1)

The semiconductor module according to claim 1, further comprising:
an isolation region of the first conductivity type that is formed separated from the first well region in an upper portion of the semiconductor substrate and to which a reference voltage is applied.

### Claim 6 (depends on 5)

The semiconductor module according to claim 5, further comprising:
a breakdown voltage region of the second conductivity type formed in an upper portion of the semiconductor substrate between the first well region and the isolation region.