# US 10,121,780 B2 · Devices related to barrier for metallization of gallium based semiconductor

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- Number: US 10,121,780 B2
- Document ID: US10121780B2
- Status: Granted
- Kind: B2
- Application number: 15/238,236
- Filed: 2016-08-16
- Published: 2016-12-08
- Granted: 2018-11-06
- Earliest claimed: 2011-11-16
- Assignees: Skyworks Solutions, Inc.
- Applicants: Skyworks Solutions, Inc.
- Inventors: Cristian Cismaru; Peter J. Zampardi, Jr.
- Web page: https://patentgrep.com/patent/US10121780B2

## CPC

- H10D 84/615: {Combinations of vertical BJTs and one or more of resistors or capacitors}
- H04M 1/026: {Details of the structure or mounting of specific components}
- H10D 1/692: {Electrodes}
- H10D 10/021: {of heterojunction BJTs [HBT]}
- H10D 10/80: Heterojunction BJTs
- H10D 10/821: {Vertical heterojunction BJTs}
- H10D 62/126: {Top-view geometrical layouts of the regions or the junctions}
- H10D 62/824: comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
- H10D 64/231: {Emitter or collector electrodes for bipolar transistors}
- H10D 84/01: Manufacture or treatment
- H10D 84/05: using Group III-V technology
- H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics}
- H10W 70/63: Vias, e.g. via plugs
- H10W 70/656: Fan-in layouts
- H10W 72/5449: {not being orthogonal to a side surface of the chip, e.g. fan-out arrangements}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H04M: TELEPHONIC COMMUNICATION (circuits for controlling other apparatus via a telephone cable and not involving telephone switching apparatus G08)
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Disclosed are structures and methods related to a barrier layer for metallization of a selected semiconductor such as indium gallium phosphide (InGaP). In some embodiments, the barrier layer can include tantalum nitride (TaN). Such a barrier layer can provide desirable features such as barrier functionality, improved adhesion of a metal layer, reduced diffusion, reduced reactivity between the metal and InGaP, and stability during the fabrication process. In some embodiments, structures formed in such a manner can be configured as an emitter of a gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) or an on-die high-value capacitance element.

## Claims

### Claim 1

A heterojunction bipolar transistor structure comprising:
a collector layer including gallium arsenide; and
a capacitor structure over the collector layer, the capacitor structure including (i) an emitter that includes indium gallium phosphide and a ledge, (ii) a metal layer over the emitter, and (iii) a tantalum nitride layer over the collector layer and the emitter such that at least a portion of the collector layer and at least a portion of the emitter are within a footprint of the tantalum nitride layer, the tantalum nitride layer being configured to separate and function as a barrier between the metal layer and the emitter, and the collector layer and the emitter being included in a heterojunction bipolar transistor.

### Claim 2 (depends on 1)

The heterojunction bipolar transistor structure of claim 1 wherein the footprint of the tantalum nitride layer is smaller than a footprint of the metal layer.

### Claim 3 (depends on 1)

The heterojunction bipolar transistor structure of claim 1 further comprising a base layer disposed between the collector layer and the emitter.

### Claim 4 (depends on 3)

The heterojunction bipolar transistor structure of claim 3 wherein the base layer includes p-type gallium arsenide and the gallium arsenide of the collector layer includes n-type gallium arsenide.

### Claim 5 (depends on 3)

The heterojunction bipolar transistor structure of claim 3 further comprising a second metal layer disposed over and in electrical communication with the base layer, the tantalum nitride layer being nested within a region defined by a footprint of the second metal layer.

### Claim 6 (depends on 1)

The heterojunction bipolar transistor structure of claim 1 wherein the tantalum nitride layer has a first side in physical contact with the emitter.

### Claim 7 (depends on 6)

The heterojunction bipolar transistor structure of claim 6 wherein the tantalum nitride layer has a second side in physical contact with the metal layer.

### Claim 8 (depends on 1)

The heterojunction bipolar transistor structure of claim 1 wherein the emitter includes an implant configured to disrupt a crystal lattice of the emitter.

### Claim 9 (depends on 1)

The heterojunction bipolar transistor structure of claim 1 wherein a capacitance density of the capacitor structure is at least 2.0 femtofarads per square micrometer.

### Claim 10

A capacitor structure comprising:
an indium gallium phosphide layer including a ledge;
a metal layer over the indium gallium phosphide layer, a tantalum nitride layer configured to separate and function as a barrier layer between the metal layer and the indium gallium phosphide layer;
a gallium arsenide layer, the indium gallium phosphide layer being disposed between the gallium arsenide layer and the tantalum nitride layer; the gallium arsenide layer, the indium gallium phosphide layer, the metal layer, and the tantalum nitride layer being included in a metal-insulator-semiconductor capacitor;
a contact to the gallium arsenide layer, a passivation structure being disposed laterally between the contact and the indium gallium phosphide layer; and
a second metal layer connected to the contact, the second metal layer being spaced apart from the metal layer, and the tantalum nitride layer being nested within a region defined by a footprint of the second metal layer.

### Claim 11 (depends on 10)

The capacitor structure of claim 10 wherein the tantalum nitride layer has a smaller footprint than the metal layer.

### Claim 12 (depends on 10)

The capacitor structure of claim 10 wherein the tantalum nitride layer is in physical contact with the indium gallium phosphide layer.

### Claim 13 (depends on 10)

The capacitor structure of claim 10 wherein a capacitance density of the capacitor is at least 2.0 femtofarads per square micrometer.

### Claim 14 (depends on 10)

The capacitor structure of claim 10 wherein the indium gallium phosphide layer includes an implant that impacts an operating voltage range of the capacitor.

### Claim 15 (depends on 10)

The capacitor structure of claim 10 wherein the indium gallium phosphide layer includes a surface in physical contact with the tantalum nitride layer and a passivation structure.

### Claim 16

A semiconductor die comprising:
a gallium arsenide layer included in a collector of a heterojunction bipolar transistor;
a semiconductor layer that includes a wide bandgap semiconductor lattice-matched to gallium arsenide, the semiconductor layer being included in an emitter of the heterojunction bipolar transistor;
a tantalum nitride layer over the collector and the emitter such that at least a portion of the collector and at least a portion of the emitter are within a footprint of the tantalum nitride layer; and
a metal layer over the semiconductor layer, the tantalum nitride layer configured to separate and function as a barrier layer between the metal layer and the semiconductor layer.

### Claim 17 (depends on 16)

The semiconductor die of claim 16 further comprising a second metal layer spaced apart from the metal layer.

### Claim 18 (depends on 17)

The semiconductor die of claim 17 wherein the tantalum nitride layer is nested within a region defined by a footprint of the second metal layer.

### Claim 19 (depends on 16)

The semiconductor die of claim 16 wherein the wide bandgap semiconductor lattice-matched to gallium arsenide includes indium gallium phosphide.

### Claim 20 (depends on 16)

The semiconductor die of claim 16 wherein the semiconductor layer includes a ledge.

### Claim 21 (depends on 16)

The semiconductor die of claim 16 further comprising another gallium arsenide layer disposed below the semiconductor layer and included in a base of the heterojunction bipolar transistor.