# US 10,121,768 B2 · Thermally enhanced face-to-face semiconductor assembly with built-in heat spreader and method of making the same

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- Number: US 10,121,768 B2
- Document ID: US10121768B2
- Status: Granted
- Kind: B2
- Application number: 15/166,185
- Filed: 2016-05-26
- Published: 2016-12-01
- Granted: 2018-11-06
- Earliest claimed: 2015-05-27
- Assignees: Bridge Semiconductor Corporation
- Applicants: Bridge Semiconductor Corporation
- Inventors: Charles W. C. Lin; Chia-Chung Wang
- Web page: https://patentgrep.com/patent/US10121768B2

## CPC

- H10W 90/00: Package configurations
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/10: Arrangements for heating
- H10W 46/00: Marks applied to devices, e.g. for alignment or identification
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/68: Shapes or dispositions thereof
- H10W 74/014: {using batch processing}
- H10W 76/01: Manufacture or treatment
- H10W 76/153: having interconnections in passages through the insulating or insulated base
- H10W 76/40: Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations H10W40/70)
- H10W 95/00: Packaging processes not covered by the other groups of this subclass
- H10P 72/743: {used as a support during manufacture of interconnect decals or build up layers}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 46/301: {for alignment}
- H10W 46/607: {Located on parts of packages, e.g. on encapsulations or on package substrates}
- H10W 70/099: {Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers}
- H10W 70/682: {comprising holes having chips therein}
- H10W 70/685: comprising multiple insulating layers
- H10W 72/0198: {batch processes}
- H10W 72/072: {of bump connectors}
- H10W 72/07207: {Temporary substrates, e.g. removable substrates}
- H10W 72/07232: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07233: {Ultrasonic bonding, e.g. thermosonic bonding}
- H10W 72/07236: {Soldering or alloying}
- H10W 72/073: {of die-attach connectors}
- H10W 72/07307: {the auxiliary member being a temporary substrate, e.g. a removable substrate}
- H10W 72/07327: {involving guiding structures, e.g. spacers or supporting members}
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/874: {On different surfaces}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 72/9413: {on encapsulations}
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/22: the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
- H10W 90/271: {the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

A face-to-face semiconductor assembly is characterized in that first and second semiconductor devices are face-to-face mounted on two opposite sides of a first routing circuitry and is further electrically connected to an interconnect board through the first routing circuitry. The interconnect board has a heat spreader to provide thermal dissipation for the second semiconductor device, and a second routing circuitry formed on the heat spreader and electrically coupled to the first routing circuitry. The first routing circuitry provides primary fan-out routing for the first and second semiconductor devices, whereas the second routing circuitry provides further fan-out wiring structure for the first routing circuitry.

## Claims

### Claim 1

A face-to-face semiconductor assembly with a built-in heat spreader, comprising:
a subassembly that includes a first semiconductor device, a balance layer and a first routing circuitry having a first surface and an opposite second surface, wherein the first semiconductor device is electrically coupled to the first routing circuitry from the first surface of the first routing circuitry and the balance layer laterally surrounds the first semiconductor device and covers the first surface of the first routing circuitry;
a second semiconductor device; and
an interconnect board that includes a heat spreader and a second routing circuitry disposed over the heat spreader, wherein the heat spreader is made entirely of a metal or an alloy and laterally extends to peripheral edges of the second routing circuitry to support the entire second routing circuitry,
wherein
(i) the second semiconductor device is attached to the heat spreader and laterally surrounded by the second routing circuitry and electrically coupled to the first routing circuitry by an array of first bumps,
(ii) the second routing circuitry is electrically coupled to the first routing circuitry by an array of second bumps, and
(iii) both the first bumps and the second bumps are disposed at the second surface of the first routing circuitry, and
wherein the second routing circuitry of the interconnect board includes first terminal pads and second terminal pads at its exterior surface facing the first routing circuitry, wherein the first terminal pads are in contact with the second bumps to be electrically coupled to the first routing circuitry, and the second terminal pads have larger pad size and pad pitch than those of the first terminal pads.

### Claim 2 (depends on 1)

The semiconductor assembly of claim 1, wherein the second semiconductor device is disposed in a cavity of the interconnect board laterally surrounded by the second routing circuitry, wherein the cavity extends into a recess in the heat spreader.

### Claim 3 (depends on 1)

The semiconductor assembly of claim 1, wherein the subassembly further includes a stiffener that is attached to an inactive surface of the first semiconductor device.

### Claim 4 (depends on 1)

The semiconductor assembly of claim 1, wherein the first routing circuitry includes at least one conductive trace laterally extending beyond peripheral edges of the first semiconductor device, whereas the second routing circuitry includes at least one conductive trace laterally extending beyond peripheral edges of the subassembly.