# US 10,121,749 B2 · Method of fabricating a post-passivation interconnect structure

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- Number: US 10,121,749 B2
- Document ID: US10121749B2
- Status: Granted
- Kind: B2
- Application number: 15/477,717
- Filed: 2017-04-03
- Published: 2017-11-23
- Granted: 2018-11-06
- Earliest claimed: 2011-12-07
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsien-Wei Chen; Hao-Yi Tsai; Mirng-Ji Lii; Chen-Hua Yu
- Web page: https://patentgrep.com/patent/US10121749B2

## CPC

- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 74/147: {the encapsulations being multilayered}
- H10W 20/49: Adaptable interconnections, e.g. fuses or antifuses
- H10W 70/654: Top-view layouts
- H10W 70/656: Fan-in layouts
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/9223: {with redistribution layers [RDL]}
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/932: {Plan-view shape, i.e. in top view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/981: {Auxiliary members, e.g. spacers}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a semiconductor device includes forming a passivation layer overlying a semiconductor substrate, and an interconnect structure overlying the passivation layer. The interconnect structure includes a landing pad region and a dummy region electrically separated from each other. A protective layer overlies the interconnect structure and includes a first opening exposing a portion of the landing pad region and a second opening exposing a portion of the dummy region. A metal layer is formed on the exposed portion of landing pad region and the exposed portion of the dummy region. A bump is formed on the metal layer overlying the landing pad region.

## Claims

### Claim 1

A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate comprising circuitry and a plurality of metal layers formed between dielectric layers operable to route electrical signals formed therein;
forming a passivation layer overlying the semiconductor substrate;
patterning the passivation layer to form a first opening, wherein a conductive pad is disposed under the first opening;
depositing a polymer layer over the passivation layer and a portion of the conductive pad;
forming a conductive layer on the polymer layer;
patterning the conductive layer to form a landing pad region electrically connected to the conductive pad and a plurality of dummy regions electrically separated from the landing pad region, wherein the plurality of dummy regions surround the landing pad region in a plan view;
depositing a metal layer on the substrate over the conductive layer;
patterning the metal layer to form an under-bump-metallization (UBM) electrically connected to the landing pad region and to form a plurality of pillars having each pillar of the plurality of pillars overlying a respective one of the plurality of dummy regions; and
forming a bump over the UBM, wherein the bump is the only bump surrounded by the plurality of pillars is the single bump.

### Claim 2 (depends on 1)

The method of claim 1, wherein the forming the conductive layer includes depositing copper.

### Claim 3 (depends on 1)

The method of claim 1, wherein depositing the polymer layer over the portion of the conductive pad includes forming an interface between the polymer layer and the conductive pad.

### Claim 4 (depends on 1)

The method of claim 1, wherein the patterning the passivation layer to form the first opening includes providing the patterned passivation layer covering a peripheral portion of the conductive pad and exposing a central portion of conductive pad.

### Claim 5 (depends on 1)

The method of claim 1, wherein the depositing the polymer layer includes depositing at least one of epoxy, polyimide, benzocyclobutene (BCB), or polybenzoxazole (PBO).

### Claim 6 (depends on 1)

The method of claim 1, wherein the depositing the polymer is performed by spin coating.

### Claim 7 (depends on 1)

The method of claim 1, wherein the patterning the conductive layer to form the landing pad region and the plurality of dummy regions forms the landing pad region and the plurality of dummy regions simultaneously.

### Claim 8 (depends on 1)

The method of claim 1, wherein the patterning the conductive layer to form the landing pad region and the plurality of dummy regions forms the landing pad region and the plurality of dummy regions of a same conductive material.

### Claim 9

A method of fabricating a semiconductor device, comprising:
forming a passivation layer overlying a semiconductor substrate;
forming a conductive layer over the semiconductor substrate and the passivation layer;
patterning the conductive layer to form a landing pad region and a plurality of dummy regions electrically separated from the landing pad region, wherein the plurality of dummy regions surround the landing pad region in a plan view;
depositing a conductive pillar over each of the plurality of dummy regions of the conductive layer; and
forming a bump over the substrate and connected to the landing pad region, wherein each of the conductive pillars is spaced a same distance from the bump.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
forming an under bump metallization (UBM) over the substrate and the patterned conductive layer, wherein the UBM is electrically connected to the landing pad region.

### Claim 11 (depends on 10)

The method of claim 10, wherein the bump is formed on the UBM.

### Claim 12 (depends on 9)

The method of claim 9, wherein the patterning the conductive layer to form the plurality of dummy regions includes forming a plurality of at least one of square-shape regions, circle-shape regions, rectangular-shape regions, or slots.

### Claim 13 (depends on 9)

The method of claim 9, wherein after patterning the conductive layer and prior to depositing the conductive pillars, forming a protective layer over at least a portion of the patterned conductive layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the protective layer interfaces with a top surface of each of the plurality of dummy regions of the patterned conductive layer.

### Claim 15 (depends on 9)

The method of claim 9, wherein the depositing the conductive pillar over each of the plurality of dummy regions includes:
depositing a metal layer;
patterning the metal layer to form the conductive pillar over each of the plurality of dummy regions and form an under-bump-metallization (UBM) layer.

### Claim 16

A method of fabricating a semiconductor device, comprising:
forming a passivation layer overlying a semiconductor substrate;
forming a first conductive layer over the passivation layer;
patterning the first conductive layer to form:
a first landing pad region and a first plurality of dummy regions electrically separated from the first landing pad region, wherein the first plurality of dummy regions surround the first landing pad region in a plan view;
a second landing pad region and a second plurality of dummy regions electrically separated from the second landing pad region, wherein the second plurality of dummy regions surround the second landing pad region in a plan view, the second plurality of dummy regions are different than the first plurality of dummy regions;
depositing a second conductive layer on the substrate over the first conductive layer;
patterning the second conductive layer to form:
a first under-bump-metallization (UBM) electrically connected to the first landing pad region, a second UBM electrically connected to the second landing pad region, a first plurality of pillars having each pillar of the first plurality of pillars overlying a respective one of the first plurality of dummy regions, and a second plurality of pillars having each pillar of the second plurality of pillars overlying a respective one of the second plurality of dummy regions; and
forming a first bump over the first UBM and a second bump over the second UBM, wherein the first plurality of pillars surrounds the first bump in the plan view and the second plurality of pillars surrounds the second bump in the plan view.

### Claim 17 (depends on 16)

The method of claim 16, wherein the first bump is a next adjacent bump to the second bump in the plan view.

### Claim 18 (depends on 16)

The method of claim 16, wherein each of the first plurality of pillars that surrounds the first bump is spaced a first distance from the first bump.

### Claim 19 (depends on 16)

The method of claim 16, wherein the depositing the second conductive layer includes one of titanium (Ti), tantalum (Ta), titanium nitride (TiN), or tantalum nitride (TaN).

### Claim 20 (depends on 19)

The method of claim 19, wherein the depositing the second conductive layer includes depositing a seed layer.