# US 10,121,744 B2 · Semiconductor devices having nonlinear bitline structures

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- Number: US 10,121,744 B2
- Document ID: US10121744B2
- Status: Granted
- Kind: B2
- Application number: 15/491,227
- Filed: 2017-04-19
- Published: 2017-08-03
- Granted: 2018-11-06
- Earliest claimed: 2014-05-21
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Yunjung Choi; Kivin Im; Dongbok Lee; Inseak Hwang
- Web page: https://patentgrep.com/patent/US10121744B2

## CPC

- H10W 20/43: Layouts of interconnections
- H10B 12/0335: {Making a connection between the transistor and the capacitor, e.g. plug}
- H10B 12/315: {with the capacitor higher than a bit line}
- H10B 12/34: {the transistor being at least partially in a trench in the substrate}
- H10B 12/482: {Bit lines}
- H10B 12/488: {Word lines}
- H10B 69/00: Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

Semiconductor devices are provided including a plurality of nonlinear bit lines formed on a substrate including a plurality of active areas; a plurality of word lines that pass through the plurality of active areas; an integral spacer that covers two sidewalls of the plurality of nonlinear bit lines and defines a plurality of spaces that expose two adjacent ones of the plurality of active areas; two conductive patterns that respectively abut on the two adjacent active areas in one of the plurality of spaces that is selected; and a contact separating insulation layer that is formed between the two conductive patterns in the one selected space.

## Claims

### Claim 1

A semiconductor device comprising:
a substrate including a first active area, a second active area and a field area;
a first bit line and a second bit line respectively having a wave shape;
a first conductive pattern on or near an end of the first active area, and a second conductive pattern on or near an end of the second active area;
a contact separating insulation layer between the first conductive pattern and the second conductive pattern; and
a first bit line spacer on the first bit line and a second bit line spacer on the second bit line,
wherein the first conductive pattern and the second conductive pattern are between the first bit line spacer and the second bit line spacer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the first bit line including a first bending portion, a second bending portion, and a third bending portion between the first bending portion and the second bending portion.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the third bending portion of the first bit line crosses the first active area.

### Claim 4 (depends on 3)

The semiconductor device of claim 3, wherein the first bending portion and the second bending portion are on the field area.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the first bending portion and the second bending portion are opposite with respect to the first active area.

### Claim 6 (depends on 5)

The semiconductor device of claim 5, wherein the first bending portion includes a highest point of the wave shape of the first bit line and the second bending portion includes a lowest point of the wave shape of the first bit line.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, further comprising a word line crossing the first bit line and the second bit line.

### Claim 8 (depends on 1)

The semiconductor device of claim 1, further comprising a word line crossing the first active area and the second active area.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, further comprising a word line crossing at least one of the first active area and the second active area.

### Claim 10 (depends on 6)

The semiconductor device of claim 6, wherein the highest point of the wave shape and the lowest point of the wave shape are disposed on the field area.

### Claim 11 (depends on 3)

The semiconductor device of claim 3, further comprising a direct contact disposed between the first active area and the third bending portion.