# US 10,121,743 B2 · Power distribution networks for a three-dimensional (3D) integrated circuit (IC) (3DIC)

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- Number: US 10,121,743 B2
- Document ID: US10121743B2
- Status: Granted
- Kind: B2
- Application number: 15/472,614
- Filed: 2017-03-29
- Published: 2018-10-04
- Granted: 2018-11-06
- Earliest claimed: 2017-03-29
- Assignees: QUALCOMM Incorporated
- Applicants: QUALCOMM Incorporated
- Inventors: Pratyush Kamal; Kambiz Samadi; Jing Xie; Yang Du
- Web page: https://patentgrep.com/patent/US10121743B2

## CPC

- H10W 90/00: Package configurations
- H10D 88/00: Three-dimensional [3D] integrated devices
- H10W 20/427: {Power or ground buses}
- H10W 80/00: Direct bonding of chips, wafers or substrates
- H10W 72/01: {Manufacture or treatment}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

Power distribution networks in a three-dimensional (3D) integrated circuit (IC) (3DIC) are disclosed. In one aspect, a voltage drop within a power distribution network in a 3DIC is reduced to reduce unnecessary power dissipation. In a first aspect, interconnect layers devoted to distribution of power within a given tier of the 3DIC are provided with an increased thickness such that a resistance of such interconnect layers is reduced relative to previously used interconnect layers and also reduced relative to other interconnect layers. Further voltage drop reductions may also be realized by placement of vias used to interconnect different tiers, and particularly, those vias used to interconnect the thickened interconnect layers devoted to the distribution of power. That is, the number, position, and/or arrangement of the vias may be controlled in the 3DIC to reduce the voltage drop.

## Claims

### Claim 1

A three-dimensional (3D) integrated circuit (IC) (3DIC), comprising:
a first IC tier comprising:
an interface layer comprising a first face; and
a first plurality of metal layers comprising a first top metal layer substantially adjacent to the first face and a first bottom metal layer spaced from the first face, wherein a thickness of the first top metal layer is at least eight times greater than a thickness of the first bottom metal layer; and
a second IC tier comprising:
a second interface layer comprising a second face positioned in a face-to-face arrangement with the first face; and
a second plurality of metal layers comprising a second top metal layer substantially adjacent to the second face and a second bottom metal layer spaced from the second face, wherein a thickness of the second top metal layer is at least eight times greater than a thickness of the second bottom metal layer.

### Claim 2 (depends on 1)

The 3DIC of claim 1, wherein the thickness of the first top metal layer is sixteen times greater than the thickness of the first bottom metal layer.

### Claim 3 (depends on 1)

The 3DIC of claim 1, wherein the thickness of the first top metal layer is thirty-two times greater than the thickness of the first bottom metal layer.

### Claim 4 (depends on 1)

The 3DIC of claim 1, further comprising a via electrically coupling the first top metal layer to the second top metal layer.

### Claim 5 (depends on 4)

The 3DIC of claim 4, wherein the via comprises a through silicon via (TSV).

### Claim 6 (depends on 4)

The 3DIC of claim 4, wherein the via comprises a through oxide via (TOV).

### Claim 7 (depends on 1)

The 3DIC of claim 1, wherein a plurality of vias electrically couple the first top metal layer to the second top metal layer.

### Claim 8 (depends on 7)

The 3DIC of claim 7, wherein the plurality of vias form two via walls around a logical circuit in the first IC tier.

### Claim 9 (depends on 7)

The 3DIC of claim 7, wherein at least one of the plurality of vias is positioned inside a logical circuit in the first IC tier.

### Claim 10 (depends on 7)

The 3DIC of claim 7, wherein a first subset of the plurality of vias is configured to be coupled to a first reference voltage source and a second subset of the plurality of vias is configured to be coupled to a second reference voltage source.

### Claim 11 (depends on 10)

The 3DIC of claim 10, wherein the plurality of vias are arranged in a plurality of rows where alternating rows are coupled to the first reference voltage source and the second reference voltage source, respectively.

### Claim 12 (depends on 11)

The 3DIC of claim 11, wherein the alternating rows are staggered relative to one another.

### Claim 13 (depends on 1)

The 3DIC of claim 1, wherein at least one of the first top metal layer and the second top metal layer comprises at least part of a power distribution path for the second IC tier.

### Claim 14 (depends on 13)

The 3DIC of claim 13, wherein both of the first top metal layer and the second top metal layer comprise at least part of the power distribution path for the second IC tier.

### Claim 15

A three-dimensional (3D) integrated circuit (IC) (3DIC) comprising:
a means for containing a first circuit comprising:
an interface layer comprising a first face; and
a first plurality of metal layers comprising a first top metal layer substantially adjacent to the first face and a first bottom metal layer spaced from the first face, wherein a thickness of the first top metal layer is at least eight times greater than a thickness of the first bottom metal layer;
a means for containing a second circuit comprising:
a second interface layer comprising a second face positioned in a face-to-face arrangement with the first face; and
a second plurality of metal layers comprising a second top metal layer substantially adjacent to the second face and a second bottom metal layer spaced from the second face, wherein a thickness of the second top metal layer is at least eight times greater than a thickness of the second bottom metal layer; and
a means for electrically coupling the first top metal layer to the second top metal layer.

### Claim 16 (depends on 15)

The 3DIC of claim 15, wherein the means for electrically coupling the first top metal layer to the second top metal layer comprises a via.