# US 10,121,738 B2 · Semiconductor constructions > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,738 B2 - Document ID: US10121738B2 - Status: Granted - Kind: B2 - Application number: 15/407,205 - Filed: 2017-01-16 - Published: 2017-05-04 - Granted: 2018-11-06 - Earliest claimed: 2011-06-06 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Alan G. Wood; Philip J. Ireland - Web page: https://patentgrep.com/patent/US10121738B2 ## CPC - H10W 20/42: Vias, e.g. via plugs - H10W 20/023: {the interconnections being through-semiconductor vias} - H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes} - H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates} - H10W 20/0245: {comprising use of blind vias during the manufacture} - H10W 20/0249: {wherein the through-semiconductor via protrudes from backsides of the chips, wafers or substrates during the manufacture} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/2125: {Top-view shapes} - H10W 20/435: {Cross-sectional shapes or dispositions of interconnections} - H10W 72/01935: {by plating, e.g. electroless plating or electroplating} - H10W 72/01938: {in gaseous form, e.g. by CVD or PVD} - H10W 72/01951: {Changing the shapes of bond pads} - H10W 72/01955: {by using masks} - H10W 72/9226: {with via interconnections} - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/9232: {with additional elements interposed between layers} - H10W 72/9415: {relative to the surface, e.g. recessed, protruding} - H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Some embodiments include methods of forming interconnects through semiconductor substrates. An opening may be formed to extend partway through a semiconductor substrate, and part of an interconnect may be formed within the opening. Another opening may be formed to extend from a second side of the substrate to the first part of the interconnect, and another part of the interconnect may be formed within such opening. Some embodiments include semiconductor constructions having a first part of a through-substrate interconnect extending partially through a semiconductor substrate from a first side of the substrate; and having a second part of the through-substrate interconnect extending from a second side of the substrate and having multiple separate electrically conductive fingers that all extend to the first part of the interconnect. ## Claims ### Claim 1 A construction, comprising: a semiconductor substrate comprising a first side and a second side in opposing relation to the first side; and a through-substrate interconnect comprising a first part and a second part coupled in series between the first side and the second side to penetrate the semiconductor substrate; wherein the first part elongates from the first side to the second side and comprises a first conductive core and a first conductive barrier covering a side surface of the first conductive core and a bottom surface, which faces the second part, of the first conductive core; wherein the second part elongates from the second side to the first side and comprises a second conductive core and a second conductive barrier covering at least a side surface of the second conductive core; and wherein the through-substrate interconnect further comprises a third part elongating from the first side to the second side to be coupled to the second part in parallel to the first part. ### Claim 2 (depends on 1) The construction of claim 1, wherein the second conductive barrier covers both a portion of a bottom surface, which faces the first part, of the second conductive core and another portion of the bottom surface, which does not face the first part, of the second conductive core. ### Claim 3 (depends on 1) The construction of claim 1, wherein the second conductive barrier does not cover a portion of a bottom surface, which faces the first part, of the second conductive core and covers another portion of the bottom surface, which does not face the first part, of the second conductive core. ### Claim 4 (depends on 1) The construction of claim 1, wherein the first part is smaller in diameter than the second part. ### Claim 5 (depends on 1) The construction of claim 1, wherein the third part comprises a third conductive core and a third conductive barrier covering a side surface of the third conductive core and a bottom surface, which faces the second part, of the third conductive core. ### Claim 6 (depends on 1) The construction of claim 1, wherein the first part and the third part are separated by a portion of the semiconductor substrate. ### Claim 7 (depends on 1) The construction of claim 1, wherein the first part and the third part are substantially equal in diameter to each other and smaller in diameter than the second part. ### Claim 8 (depends on 1) The construction of claim 1, further comprising a conductive material on the semiconductor substrate, the conductive material being connected to each of top surfaces of the first conductive core and the third conductive core. ### Claim 9 A construction, comprising: a semiconductor substrate comprising a first side and a second side in opposing relation to the first side; and a through-substrate interconnect embedded in a hole penetrating the semiconductor substrate, the through-substrate interconnect comprising a first conductive core formed on the first side, a second conductive core formed on the second side, a first conductive barrier formed between the first conductive core and the second conductive core, a second conductive barrier lining between a portion of a side surface of the hole and a side surface of the first conductive core and a third conductive barrier lining between a remaining portion of the side surface of the hole and a side surface of the second conductive core; wherein the first conductive barrier and the second conductive barrier are continuously formed as a single film; and wherein the third conductive barrier is formed separately from the single film. ### Claim 10 (depends on 9) The construction of claim 9, wherein the hole comprises a first portion surrounded by the portion of the side surface and a second portion surrounded by the remaining portion of the side surface, the first portion is different in diameter than the second portion. ### Claim 11 (depends on 9) The construction of claim 9, wherein the through-substrate interconnect further comprises a fourth conductive barrier formed on the first conductive barrier between the first conductive core and the second conductive core. ### Claim 12 (depends on 11) The construction of claim 11, wherein the third conductive barrier and the fourth conductive barrier are continuously formed as another single film. ### Claim 13 A construction, comprising: a semiconductor substrate comprising a first side and a second side in opposing relation to the first side; and a through-substrate interconnect comprising a first part and a second part coupled in series between the first side and the second side to penetrate the semiconductor substrate; wherein the first part elongates from the first side to the second side and comprises a first conductive core and a first conductive barrier covering a side surface of the first conductive core and a bottom surface, which faces the second part, of the first conductive core; wherein the second part elongates from the second side to the first side and comprises a second conductive core and a second conductive barrier covering at least a side surface of the second conductive core; and wherein the second conductive barrier covers both a portion of a bottom surface, which faces the first part, of the second conductive core and another portion of the bottom surface, which does not face the first part, of the second conductive core. ### Claim 14 A construction, comprising: a semiconductor substrate comprising a first side and a second side in opposing relation to the first side; and a through-substrate interconnect embedded in a hole penetrating the semiconductor substrate, the through-substrate interconnect comprising a first conductive core formed on the first side, a second conductive core formed on the second side, a first conductive barrier formed between the first conductive core and the second conductive core, a second conductive barrier lining between a portion of a side surface of the hole and a side surface of the first conductive core and a third conductive barrier lining between a remaining portion of the side surface of the hole and a side surface of the second conductive core; and wherein the through-substrate interconnect further comprises a fourth conductive barrier formed on the first conductive barrier between the first conductive core and the second conductive core. ### Claim 15 (depends on 14) The construction of claim 14, wherein the first conductive barrier and the second conductive barrier are continuously formed as a single film and the third conductive barrier and the fourth conductive barrier are continuously formed as another single film.