# US 10,121,736 B2 · Method of fabricating packaging layer of fan-out chip package

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,736 B2
- Document ID: US10121736B2
- Status: Granted
- Kind: B2
- Application number: 15/876,210
- Filed: 2018-01-22
- Published: 2018-05-24
- Granted: 2018-11-06
- Earliest claimed: 2015-12-23
- Assignees: Powertech Technology Inc.
- Applicants: Powertech Technology Inc.
- Inventors: Kuo-Ting Lin; Chia-Wei Chang
- Web page: https://patentgrep.com/patent/US10121736B2

## CPC

- H10W 70/635: {Through-vias}
- H10W 70/09: extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
- H10W 70/095: {of vias therein}
- H10W 70/614: {the multiple chips being integrally enclosed}
- H10W 72/90: Bond pads, in general
- H10W 74/019: {using temporary auxiliary substrates (H10W74/017 takes precedence)}
- H10W 90/00: Package configurations
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/652: Cross-sectional shapes
- H10W 70/655: Fan-out layouts
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/241: {Dispositions, e.g. layouts}
- H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/823: {Interconnections through encapsulations, e.g. pillars through molded resin on a lateral side a chip}
- H10W 72/874: {On different surfaces}
- H10W 72/9413: {on encapsulations}
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/722: {between stacked chips}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.

## Claims

### Claim 1

A method of fabricating a packaging layer of an fan-out chip package comprising:
disposing a chip on a temporary carrier, wherein the chip has an active surface facing the temporary carrier, a back surface opposite the active surface, and a plurality of sides formed between the active surface and the back surface, the active surface having a plurality of bond pads;
forming an encapsulation on the temporary carrier to encapsulate the chip, wherein the encapsulation has a peripheral surface formed according to a surface of the temporary carrier;
grinding the encapsulation and the chip to form the back surface of the chip and a back surface of the encapsulation, wherein the back surface of the chip and the back surface of the encapsulation are coplanar to each other;
debonding the encapsulation and the chip from the temporary carrier;
forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation;
patterning the first passivation layer to form a plurality of fan-in openings and a plurality of fan-out openings on the first passivation layer, wherein the fan-in openings are configured to expose the bond pads and the fan-out openings are configured to expose part of the peripheral surface;
forming a redistribution layer on the first passivation layer, wherein a part of the redistribution layer are formed in the plurality of fan-in openings and another part of the redistribution layer are formed in the plurality of fan-out openings, wherein the part of the redistribution layer formed in the plurality of fan-in openings are configured to electrically couple to the plurality of bond pads of the chip and the another part of the redistribution layer formed in the plurality of fan-out openings are fan-out pads configured to physically couple to the peripheral surface of the encapsulation, wherein the redistribution layer has a dummy pattern formed on the first passivation layer;
forming a second passivation layer on the first passivation layer and the redistribution wiring layer;
forming a plurality of vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and
disposing a plurality of dummy terminals on the dummy pattern.

### Claim 2 (depends on 1)

The method as claimed in claim 1, wherein forming a plurality of vertical connectors within the encapsulation to correspondingly couple to the fan-out pads comprises:
forming a plurality of through holes on the encapsulation, each of the through holes being aligned to a corresponding fan-out pad; and
filling the through holes with a conductive material to form the vertical connectors.

### Claim 3 (depends on 1)

The method as claimed in claim 1, further comprising:
disposing a plurality of connecting terminals on the fan-out pads, wherein the plurality of connecting terminals are protruding from the second passivation layer.

### Claim 4 (depends on 3)

The method as claimed in claim 3, further comprising:
forming a non-conductive adhesive layer on the second passivation layer to encapsulate the connecting terminals.

### Claim 5 (depends on 3)

The method as claimed in claim 3, further comprising:
forming a plurality of dummy pads on the back surface of the encapsulation and/or the back surface of the chip, wherein each of the plurality of dummy pads are vertically aligned to a corresponding dummy terminal.

### Claim 6 (depends on 1)

The method as claimed in claim 1, wherein the temporary carrier is a wafer or a panel and the encapsulation takes a shape of the temporary carrier when formed.

### Claim 7 (depends on 1)

The method as claimed in claim 1, further comprising:
laminating a plurality of packaging layers on each other to form the fan-out chip package.

### Claim 8 (depends on 7)

The method as claimed in claim 7, further comprising:
performing singulation on the fan-out chip package to form a plurality of individual fan-out chip packages.