# US 10,121,731 B2 · Semiconductor device

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- Number: US 10,121,731 B2
- Document ID: US10121731B2
- Status: Granted
- Kind: B2
- Application number: 15/290,899
- Filed: 2016-10-11
- Published: 2017-04-20
- Granted: 2018-11-06
- Earliest claimed: 2015-10-19
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Sang Cheon Park; Won Il Lee; Chajea Jo; Taeje Cho
- Web page: https://patentgrep.com/patent/US10121731B2

## CPC

- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 20/0234: {comprising etching via holes that stop on pads or on electrodes}
- H10W 20/0242: {comprising etching via holes from the back sides of the chips, wafers or substrates}
- H10W 20/0245: {comprising use of blind vias during the manufacture}
- H10W 20/2125: {Top-view shapes}
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/43: Layouts of interconnections
- H10W 20/4421: {the principal metal being copper}
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/01935: {by plating, e.g. electroless plating or electroplating}
- H10W 72/242: {relative to the surface, e.g. recessed, protruding}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/29: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/9415: {relative to the surface, e.g. recessed, protruding}
- H10W 72/942: {relative to underlying supporting features, e.g. bond pads, RDLs or vias}
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 90/00: Package configurations
- H10W 90/26: the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
- H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device includes a semiconductor chip having an active surface and a non-active surface opposite to the active surface, an upper insulating layer provided on the non-active surface of semiconductor chip, and a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively. The connection pad has a first surface exposed outside the upper insulating layer and a second surface opposite to the first surface and facing the semiconductor chip. The first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor chip having an active surface and a non-active surface opposite to the active surface;
an upper insulating layer provided on the non-active surface of the semiconductor chip;
a via and a connection pad penetrating the semiconductor chip and the upper insulating layer, respectively, wherein the connection pad and the via comprise portions of a continuously formed same first material;
a pad insulating layer provided on the non-active surface of the semiconductor chip, the pad insulating layer including a top surface contacting the first material forming a bottom surface of the connection pad, a first side surface contacting the first material forming a side of the via, and a second side surface contacting the upper insulating layer; and
an external terminal provided directly on and electrically connected to the connection pad and vertically aligned with the via, the external terminal comprising solder,
wherein the connection pad has a first surface exposed with respect to the upper insulating layer, a second surface opposite to the first surface and facing the semiconductor chip, and a first sidewall extending in a vertical direction from the first surface to the second surface,
wherein the first sidewall contacts the upper insulating layer,
wherein the upper insulating layer is a continuous layer that extends from the first sidewall to contact a second sidewall of an adjacent connection pad, and
wherein the first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the connection pad is provided in the upper insulating layer, and
wherein a thickness of the connection pad is smaller than a thickness of the upper insulating layer.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the connection pad is provided in the upper insulating layer, and
wherein a thickness of the connection pad is equal to or greater than a thickness of the upper insulating layer.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein a width of the connection pad is greater than a width of the via.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, further comprising:
a lower insulating layer disposed on the active surface; and
an external pad disposed on the lower insulating layer,
wherein the via penetrates the lower insulating layer so as to be electrically connected to the external-pad.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the connection pad and the via are integrally formed.

### Claim 7 (depends on 6)

The semiconductor device of claim 6, wherein the connection pad and the via are formed of a same plating material.

### Claim 8

A semiconductor device comprising:
a semiconductor chip having a first surface and a second surface opposite to the first surface;
an upper insulating layer provided on the first surface of the semiconductor chip;
a lower insulating layer provided on the second surface of the semiconductor chip;
an external pad disposed on the lower insulating layer and contacting the lower insulating layer;
a via-hole penetrating the semiconductor chip and extending into the lower insulating layer to the external pad;
a connection pad provided on the first surface;
a via connected to the connection pad and provided in the via-hole so as to be electrically connected to the external pad, wherein the connection pad and the via comprise portions of a continuously formed same first material;
a pad insulating layer provided on the first surface of the semiconductor chip, the pad insulating layer including a top surface contacting the first material forming a bottom surface of the connection pad, a first side surface contacting the first material forming a side of the via, and a second side surface contacting the upper insulating layer; and
an external terminal provided directly on and electrically connected to the connection pad and vertically aligned with the via, the external terminal comprising solder,
wherein the connection pad has a bottom directly connected to the via and has a top surface opposite to the bottom, and
wherein the top surface of the connection pad is coplanar with a top surface of the upper insulating layer.

### Claim 9 (depends on 8)

The semiconductor device of claim 8, wherein the via and the connection pad are formed of the same metal material, and
wherein the same metal material includes copper.

### Claim 10 (depends on 8)

The semiconductor device of claim 8, wherein the upper insulating layer has a recess region recessed from the top surface of the upper insulating layer toward the first surface of the semiconductor chip, and
wherein the connection pad is provided in the recess region.

### Claim 11 (depends on 8)

The semiconductor device of claim 8, further comprising:
a via insulating layer provided between the via and a sidewall of the via-hole to surround the via.

### Claim 12 (depends on 8)

The semiconductor device of claim 8, wherein the connection pad and the via are integrally formed of a same plating material.

### Claim 13

A semiconductor device comprising:
a semiconductor chip having an active surface and a non-active surface opposite to the active surface;
an upper insulating layer provided on the non-active surface of the semiconductor chip;
a lower insulating layer provided on the active surface of the semiconductor chip;
a connection pad provided on the non-active surface of the semiconductor chip;
a via connected to the connection pad and provided in a via-hole, wherein the connection pad and the via comprise portions of a continuously formed same first material;
a pad insulating layer provided on the non-active surface of the semiconductor chip, the pad insulating layer including a top surface contacting the first material forming a bottom surface of the connection pad, a first side surface contacting the first material forming a side of the via, and a second side surface contacting the upper insulating layer; and
an external terminal provided directly on and electrically connected to the connection pad and vertically aligned with the via, the external terminal comprising solder,
wherein the connection pad has a first surface exposed outside the upper insulating layer, a second surface opposite to the first surface and facing the semiconductor chip, and a first sidewall extending in a vertical direction from the first surface to the second surface and contacting the upper insulating layer,
wherein the upper insulating layer is a continuous layer that extends from the first sidewall to contact a second sidewall of an adjacent connection pad, and
wherein the first surface of the connection pad is coplanar with an upper surface of the upper insulating layer.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein the via-hole penetrates into the lower insulating layer.

### Claim 15 (depends on 13)

The semiconductor device of claim 13, wherein the upper insulating layer has a recess region recessed from a top surface of the upper insulating layer toward the non-active surface of the semiconductor chip, and
wherein the connection pad is provided in the recess region.

### Claim 16 (depends on 13)

The semiconductor device of claim 13, wherein the via-hole penetrates the semiconductor chip and extends to the lower insulating layer.

### Claim 17 (depends on 13)

The semiconductor device of claim 13, further comprising:
a via insulating layer provided between the via and a sidewall of the via-hole to surround the via.

### Claim 18 (depends on 13)

The semiconductor device of claim 13, wherein the connection pad and the via are integrally formed of a same plating material.

### Claim 19 (depends on 13)

The semiconductor device of claim 13, further comprising:
a lower insulating layer disposed on the active surface; and
an external pad disposed on the lower insulating layer and contacting the lower insulating layer,
wherein the via penetrates the lower insulating layer so as to be electrically connected to the external pad.