# US 10,121,722 B1 · Architecture material and process to improve thermal performance of the embedded die package

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- Number: US 10,121,722 B1
- Document ID: US10121722B1
- Status: Granted
- Kind: B1
- Application number: 15/721,880
- Filed: 2017-09-30
- Granted: 2018-11-06
- Earliest claimed: 2017-09-30
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Chandra M. Jha; Eric J. Li; Zhaozhi Li; Robert M. Nickerson
- Web page: https://patentgrep.com/patent/US10121722B1

## CPC

- H10W 40/25: characterised by their materials
- H10W 40/228: {the projecting parts being wire-shaped or pin-shaped}
- H10W 72/00: Interconnections or connectors in packages
- H10W 74/117: {the substrate having spherical bumps for external connection}
- H10W 90/00: Package configurations
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/635: {Through-vias}
- H10W 72/07332: {Compression bonding, e.g. thermocompression bonding}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/07354: {changes in dispositions}
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/321: {Structures or relative sizes of die-attach connectors}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/332: {Plan-view shape, i.e. in top view}
- H10W 72/347: {Dispositions of multiple die-attach connectors}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/353: {not comprising solid metals or solid metalloids, e.g. ceramics}
- H10W 72/387: {Flow barriers}
- H10W 72/931: {Shapes of bond pads}
- H10W 74/10: characterised by their shape or disposition
- H10W 74/142: {the encapsulations exposing the passive side of the semiconductor body}
- H10W 90/288: {characterised by arrangements for thermal management of the stacked chips}
- H10W 90/401: {characterised by multiple insulating or insulated package substrates, interposers or RDLs}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/722: {between stacked chips}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A device package and a method of forming the device package are described. The device package has a package layer disposed on a substrate. The package layer includes a mold layer surrounding solder balls and a die. The device package also has a trench disposed in the mold layer to surround the die of the package layer. The device package further includes a conductive layer disposed on a top surface of the die. The conductive layer is disposed over the top surface of the die and in the trench of the package layer. The trench may have a specified distance between the die edges, and a specified width and a specified depth based on the conductive layer. The device package may include an interposer with solder balls disposed on the conductive layer and above the package layer, and an underfill layer disposed between the interposer and the package layer.

## Claims

### Claim 1

A device package, comprising:
a package layer disposed on a substrate, wherein the package layer includes a mold layer surrounding a first plurality of solder balls and a die;
a trench disposed in the mold layer to surround the die of the package layer; and
a conductive layer disposed on a top surface of the die, wherein the conductive layer is disposed over the top surface of the die and in the trench of the package layer.

### Claim 2 (depends on 1)

The device package of claim 1, wherein the trench has a specified distance between each of the edges of the die.

### Claim 3 (depends on 1)

The device package of claim 1, wherein the trench has a specified width and a specified depth based on the conductive layer.

### Claim 4 (depends on 1)

The device package of claim 1, further comprising:
an interposer with a second plurality of solder balls disposed on the conductive layer and above the package layer; and
an underfill layer disposed between a bottom surface of the interposer and a top surface of the package layer.

### Claim 5 (depends on 4)

The device package of claim 4, further comprising:
a memory with a third plurality of solder balls disposed on the interposer, wherein the third solder balls electrically couple the memory and the interposer; and
a fourth plurality of solder balls disposed on a bottom surface of the substrate.

### Claim 6 (depends on 5)

The device package of claim 5, wherein the substrate is disposed on a motherboard, and wherein the fourth plurality of solder balls electrically couple the substrate and the motherboard.

### Claim 7 (depends on 1)

The device package of claim 1, further comprising a second memory with a fifth plurality of solder balls disposed on the conductive layer and above the package layer.

### Claim 8 (depends on 1)

The device package of claim 1, wherein the conductive layer includes one or more different materials, and wherein the conductive layer is disposed on the top surface of the die with one or more different patterns.

### Claim 9 (depends on 1)

The device package of claim 1, wherein the substrate is a printed circuit board.

### Claim 10

A method of forming a device package, comprising:
disposing a package layer on a substrate, wherein the package layer includes a mold layer surrounding a first plurality of solder balls and a die;
disposing a trench in the mold layer to surround the die of the package layer; and
disposing a conductive layer on a top surface of the die, wherein the conductive layer is disposed over the top surface of the die and in the trench of the package layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the trench has a specified distance between each of the edges of the die.

### Claim 12 (depends on 10)

The method of claim 10, wherein the trench has a specified width and a specified depth based on the conductive layer.

### Claim 13 (depends on 10)

The method of claim 10, further comprising:
disposing an interposer with a second plurality of solder balls on the conductive layer and above the package layer; and
disposing an underfill layer between a bottom surface of the interposer and a top surface of the package layer.

### Claim 14 (depends on 13)

The method of claim 13, further comprising:
disposing a memory with a third plurality of solder balls on the interposer, wherein the third solder balls electrically couple the memory and the interposer; and
disposing a fourth plurality of solder balls on a bottom surface of the substrate.

### Claim 15 (depends on 14)

The method of claim 14, wherein the substrate is disposed on a motherboard, and wherein the fourth plurality of solder balls electrically couple the substrate and the motherboard.

### Claim 16 (depends on 10)

The method of claim 10, further comprising disposing a second memory with a fifth plurality of solder balls on the conductive layer and above the package layer.

### Claim 17 (depends on 10)

The method of claim 10, wherein the conductive layer includes one or more different materials, and wherein the conductive layer is disposed on the top surface of the die with one or more different patterns.

### Claim 18 (depends on 10)

The method of claim 10, wherein the substrate is a printed circuit board.

### Claim 19

A device package, comprising:
a package layer disposed on a substrate, wherein the package layer includes a mold layer surrounding a first plurality of solder balls and a die;
a trench disposed in the mold layer to surround the die of the package layer;
a conductive layer disposed on a top surface of the die, wherein the conductive layer is disposed over the top surface of the die and in the trench of the package layer;
an interposer with a second plurality of solder balls disposed on the conductive layer and above the package layer;
an underfill layer disposed between a bottom surface of the interposer and a top surface of the package layer; and
a memory with a third plurality of solder balls disposed on the interposer, wherein the third solder balls electrically couple the memory and the interposer, and wherein a fourth plurality of solder balls are disposed on a bottom surface of the substrate.

### Claim 20 (depends on 19)

The device package of claim 19, wherein the trench has a specified distance between each of the edges of the die.

### Claim 21 (depends on 19)

The device package of claim 19, wherein the trench has a specified width and a specified depth based on the conductive layer.

### Claim 22 (depends on 19)

The device package of claim 19, wherein the substrate is disposed on a motherboard, and wherein the fourth plurality of solder balls electrically couple the substrate and the motherboard.

### Claim 23 (depends on 19)

The device package of claim 19, wherein the conductive layer includes one or more different materials.

### Claim 24 (depends on 19)

The device package of claim 19, wherein the conductive layer is disposed on the top surface of the die with one or more different patterns.

### Claim 25 (depends on 19)

The device package of claim 19, wherein the substrate is a printed circuit board.