# US 10,121,721 B2 · Heat dissipation bump electrode for chip on film > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,721 B2 - Document ID: US10121721B2 - Status: Granted - Kind: B2 - Application number: 14/965,897 - Filed: 2015-12-10 - Published: 2016-06-16 - Granted: 2018-11-06 - Earliest claimed: 2014-12-12 - Assignees: Lapis Semiconductor Co., Ltd. - Applicants: LAPIS Semiconductor Co., Ltd. - Inventors: Hiroyoshi Ichikura - Web page: https://patentgrep.com/patent/US10121721B2 ## CPC - H10W 40/228: {the projecting parts being wire-shaped or pin-shaped} - G02F 1/1333: Constructional arrangements; {Manufacturing methods}(G02F1/135, G02F1/136 take precedence) - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 3/3685: {Details of drivers for data electrodes} - G09G 3/3696: {Generation of voltages supplied to electrode drivers} - G09G 2300/0426: Layout of electrodes and connections - H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes - H10W 72/248: {Top-view layouts, e.g. mirror arrays} - H10W 72/265: {Providing thermal transfer, e.g. thermal bumps} - H10W 72/267: {Multiple bump connectors having different functions} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A dummy bump electrode for heat-dissipating is provided on a surface of a semiconductor chip. The semiconductor chip is mounted on a wiring substrate. A lead line is formed on the wiring substrate. The heat-dissipating bump electrode and a lead line are connected to each other through a heat dissipation pattern, thereby efficiency of the heat dissipation is improved. ## Claims ### Claim 1 A semiconductor package, comprising: a semiconductor chip carrying a bump electrode formed thereon and including a semiconductor substrate and at least one electrode layer; a wiring substrate carrying a lead line connected to said bump electrode, the lead line being formed on a facing surface of the wiring substrate facing the semiconductor chip; at least one heat dissipation bump electrode for dissipating heat disposed on the semiconductor chip, a surface of said semiconductor substrate and said electrode layer being connected to each other through a metallic material at a location directly below said heat dissipation bump electrode within the surface of said semiconductor substrate; and at least one heat dissipation pattern formed on said facing surface of the wiring substrate and being electrically connected to said heat dissipation bump electrode, to dissipate heat from the semiconductor chip, wherein the heat dissipation bump electrode is formed over or around a high temperature area on the semiconductor chip, the high temperature area having a temperature higher than a predetermined threshold value during operation of the semiconductor chip. ### Claim 2 (depends on 1) The semiconductor package according to claim 1, wherein said heat dissipation pattern is electrically connected to said heat dissipation bump electrode and said lead line. ### Claim 3 (depends on 2) The semiconductor package according to claim 2, wherein said lead line connected to said heat dissipation pattern in said wiring substrate is a power supply line for supplying a source voltage to said semiconductor chip or a grounding line. ### Claim 4 (depends on 1) The semiconductor package according to claim 1, wherein said electrode layer includes first to fourth electrode layers layered and insulating layers which are layered such a manner that each insulating layer is sandwiched between a pair of neighboring electrode layers, wherein the surface of said semiconductor substrate and said first electrode layer are connected to each other through a metallic material at a location directly below said heat dissipation bump electrode within the surface of said semiconductor substrate, and wherein said second to fourth electrode layers are connected in serial order through metallic materials at a location other than directly below said heat dissipation bump electrode. ### Claim 5 (depends on 1) The semiconductor package according to claim 1, wherein said electrode layer includes first to fourth electrode layers layered and insulating layers which are layered such a manner each insulating layer is sandwiched between a pair of neighboring electrode layers, and wherein the surface of said semiconductor substrate and said first to fourth electrode layers are connected in serial order through a metallic materials at a location directly below said heat dissipation bump electrode within the surface of said semiconductor substrate. ### Claim 6 (depends on 1) The semiconductor package according to claim 1, wherein said bump electrode is electrically connected to a circuit formed in said semiconductor chip within said semiconductor chip, and wherein said heat dissipation bump electrode is a metallic bump electrically not connected to the circuit formed in said semiconductor chip within said semiconductor chip. ### Claim 7 (depends on 1) The semiconductor package according to claim 1, wherein said heat dissipation bump electrode is formed at a position closer to said high temperature area than said bump electrode on the semiconductor chip so as to surround said high temperature area. ### Claim 8 (depends on 1) The semiconductor package according to claim 1, further comprising: an LCD driving circuit for driving an LCD panel wherein the LCD driving circuit is formed on the surface of said semiconductor substrate; and a gamma buffer formed at position corresponding to said high temperature area on the surface of said semiconductor substrate wherein the gamma buffer amplifies a reference voltage as a reference of gradation voltages distributing along a gamma characteristics of an image. ### Claim 9 (depends on 1) The semiconductor package according to claim 1, wherein said wiring substrate is a filmy flexible wiring substrate.