# US 10,121,720 B2 · Semiconductor device, corresponding apparatus and method

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,720 B2
- Document ID: US10121720B2
- Status: Granted
- Kind: B2
- Application number: 15/617,561
- Filed: 2017-06-08
- Published: 2018-07-05
- Granted: 2018-11-06
- Earliest claimed: 2017-01-03
- Assignees: STMicroelectronics S.r.l.
- Applicants: Stmicroelectronics S.R.L.
- Inventors: Federico Giovanni Ziglioli
- Web page: https://patentgrep.com/patent/US10121720B2

## CPC

- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/25: characterised by their materials
- H10W 40/778: {in encapsulations}
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 42/276: {the arrangements being on an external surface of the package, e.g. on the outer surface of an encapsulation}
- H10W 70/023: {Connecting or disconnecting interconnections thereto or therefrom, e.g. connecting bond wires or bumps}
- H10W 70/417: {Bonding materials between chips and die pads}
- H10W 70/421: {Shapes or dispositions}
- H10W 70/427: {Bent parts}
- H10W 74/016: {using moulds}
- H10W 74/124: {the encapsulations having cavities other than that occupied by chips}
- H10W 74/129: {forming a chip-scale package [CSP]}
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/6523: {for connecting to pads at different heights at the same side of the package substrate, interposer or RDL}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/551: {Materials of bond wires}
- H10W 72/853: {On the same surface}
- H10W 72/874: {On different surfaces}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 72/922: {Bond pads being integral with underlying chip-level interconnections}
- H10W 72/9413: {on encapsulations}
- H10W 90/00: Package configurations
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W 90/755: {between a chip and a laterally-adjacent insulating package substrate, interpose or RDL}
- H10W 90/756: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A semiconductor device, such as a semiconductor power device, includes: a semiconductor die having a semiconductor die front surface, a package formed onto the semiconductor die, the package having a portion facing the front surface of the semiconductor die, and a thermally-conductive layer including graphene over the front portion of the package facing the front surface of the semiconductor die.

## Claims

### Claim 1

A semiconductor device, comprising:
a semiconductor die having a surface;
a conductive member having first and second ends;
a package material formed on the semiconductor die, the package material having a top surface, the first end of the conductive member being on the top surface of the package material, wherein the second end is outside of the package material; and
a thermally-conductive layer contacting the top surface of the package material and the first end of the conductive member, the thermally-conductive layer facing the surface of the semiconductor die, the thermally-conductive layer including graphene.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the package material includes a recessed portion and the thermally-conductive layer is located in the recessed portion.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the thermally-conductive layer is in contact with or in the vicinity of the surface of the semiconductor die at the recessed portion.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the conductive member is a thermally-conductive member.

### Claim 5 (depends on 1)

The semiconductor device of claim 1, wherein the thermally-conductive layer covers a majority of the top surface of the package material, wherein the thermally-conductive layer provides an electromagnetic interference shield for the semiconductor die.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, comprising a die mounting pad coupled to the semiconductor die and configured to support the semiconductor die.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, comprising a heat sink arranged in thermal exchange relationship with the thermally-conductive layer.

### Claim 8

An apparatus, comprising: a support substrate; and at least one semiconductor package including: a semiconductor die; a molding compound covering at least a portion of the semiconductor die; a conductive member having a first end on a top surface of the molding compound and a second end configured to be coupled to another device outside of the molding compound; and a thermally-conductive layer contacting the molding compound and the first end of the conductive member, the thermally-conductive layer including graphene.

### Claim 9 (depends on 8)

The apparatus of claim 8, wherein the molding compound includes a recess at a surface of the semiconductor die, the thermally-conductive layer covering the molding compound and the surface of the semiconductor die at the recess.

### Claim 10 (depends on 8)

The apparatus of claim 8, wherein the molding compound includes a recess that exposes the semiconductor die, the thermally-conductive layer abutting the semiconductor die in the recess.

### Claim 11 (depends on 8)

The apparatus of claim 8, comprising a plurality of conductive members having first ends on the top surface of the molding compound and second ends configured to be coupled to another device, the thermally-conductive layer on the first ends of the plurality of conductive members.

### Claim 12 (depends on 8)

The apparatus of claim 8, wherein the thermally-conductive layer covers a majority of the top surface of the molding compound.

### Claim 13

A method comprising: forming a semiconductor package that includes a package material that encapsulates at least partially a semiconductor die, the semiconductor package including a conductive member having a first end on a top surface of the package material and a second end arranged laterally with respect to the package material and outside of the package material; and forming a thermally-conductive layer including graphene contacting the top surface of the package material and the first end of the conductive member.

### Claim 14 (depends on 13)

The method of claim 13, wherein forming the thermally-conductive layer comprises printing a graphene-containing ink on the top surface of the package material and the first end of the conductive member.

### Claim 15 (depends on 14)

The method of claim 14, comprising after printing the graphene-containing ink on the top surface of the package material, compressing the graphene-containing ink.

### Claim 16 (depends on 13)

The method of claim 13, wherein forming the semiconductor package includes forming the semiconductor package to having a recess in the package material, the recess facing a surface of the semiconductor die.

### Claim 17 (depends on 16)

The method of claim 16, wherein forming the thermally-conductive layer comprises forming a conformal layer over a surface of the semiconductor package that includes the recess of the package.

### Claim 18 (depends on 15)

The method of claim 15, wherein forming the thermally-conductive layer comprises printing a thermally-conductive ink on a majority of the top surface of the package material.

### Claim 19 (depends on 15)

The method of claim 15, comprising coupling a heat sink to the thermally-conductive layer.