# US 10,121,718 B2 · Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer

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- Number: US 10,121,718 B2
- Document ID: US10121718B2
- Status: Granted
- Kind: B2
- Application number: 14/885,202
- Filed: 2015-10-16
- Published: 2016-05-05
- Granted: 2018-11-06
- Earliest claimed: 2014-11-03
- Assignees: Qorvo US, Inc.
- Applicants: RF Micro Devices, Inc.
- Inventors: Dirk Robert Walter Leipold; Julio C. Costa; Baker Scott; George Maxim
- Web page: https://patentgrep.com/patent/US10121718B2

## CPC

- H10W 74/124: {the encapsulations having cavities other than that occupied by chips}
- H01Q 1/50: Structural association of antennas with earthing switches, lead-in devices or lightning protectors
- H05K 1/0203: {Cooling of mounted components (H05K1/0272 takes precedence)}
- H05K 1/181: associated with surface mounted components
- H10P 14/6329: {using physical ablation of a target, e.g. physical vapour deposition or pulsed laser deposition}
- H10P 14/6342: {Liquid deposition, e.g. spin-coating, sol-gel techniques or spray coating}
- H10P 52/00: Grinding, lapping or polishing of wafers, substrates or parts of devices
- H10P 72/74: {using temporarily an auxiliary support}
- H10W 40/10: Arrangements for heating
- H10W 40/22: characterised by their shape, e.g. having conical or cylindrical projections
- H10W 40/251: {Organics}
- H10W 40/259: {Ceramics or glasses (H10W40/254, H10W40/257, H10W40/255, H10W40/251, H10W40/253 take precedence)}
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 74/016: {using moulds}
- H10W 74/121: {by multiple encapsulations, e.g. by a thin protective coating and a thick encapsulation}
- H10W 74/43: comprising oxides, nitrides or carbides, e.g. ceramics or glasses
- H10W 74/47: comprising organic materials, e.g. plastics or resins
- H10W 76/43: Gaseous fillings
- H10D 1/20: Inductors
- H10D 1/47: Resistors having no potential barriers
- H10D 1/68: Capacitors having no potential barriers
- H10P 50/642: {Chemical etching}
- H10P 72/7416: {used during dicing or grinding}
- H10P 72/7422: {used to protect an active side of a device or wafer}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10W 20/496: {Capacitor integral with wiring layers}
- H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers}
- H10W 20/498: {Resistive arrangements or effects of, or between, wiring layers}
- H10W 72/072: {of bump connectors}
- H10W 72/073: {of die-attach connectors}
- H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 74/114: {by a substrate and the encapsulations}
- H10W 74/15: on active surfaces of flip-chip devices, e.g. underfills
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H01Q: ANTENNAS, i.e. RADIO AERIALS (radiators or antennas for microwave heating H05B6/72)
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

## Claims

### Claim 1

A printed circuit module comprising:
a printed circuit substrate;
a thinned die attached to the printed circuit substrate and having at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer; and
an outer protective layer over the at least one deep well, wherein the outer protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.

### Claim 2 (depends on 1)

The circuit board of claim 1 further including an inner protective layer that resides between the printed circuit substrate and the thinned die.

### Claim 3 (depends on 2)

The printed circuit module of claim 2 wherein the inner protective layer and the outer protective layer are made of a polymer compound.

### Claim 4 (depends on 3)

The printed circuit module of claim 3 wherein the outer protective layer is made of ceramic.

### Claim 5 (depends on 4)

The printed circuit module of claim 4 wherein the ceramic is aluminum nitride.

### Claim 6 (depends on 4)

The printed circuit module of claim 4 wherein the ceramic is silicon nitride.

### Claim 7 (depends on 2)

The printed circuit module of claim 2 wherein the inner protective layer is made of ceramic.

### Claim 8 (depends on 1)

The printed circuit module of claim 1 wherein the at least one deep well is a deep N-well.

### Claim 9 (depends on 1)

The printed circuit module of claim 1 wherein the outer protective layer is made of a polymer compound.

### Claim 10 (depends on 1)

The printed circuit module of claim 1 wherein a thickness of the outer protective layer ranges from about 100 μm to around 500 μm.

### Claim 11 (depends on 1)

The printed circuit module of claim 1 wherein the thermal conductivity of the protective layer ranges from about 10 W/mK to around 50 W/mK.

### Claim 12 (depends on 1)

The printed circuit module of claim 1 wherein the thermal conductivity of the outer protective layer ranges from around about 50 W/mK to around about 6600 W/mK.

### Claim 13 (depends on 1)

The printed circuit module of claim 1 wherein the outer protective layer covers a gas filled space over at least a portion of the thinned die.

### Claim 14 (depends on 13)

The printed circuit module of claim 13 wherein the at least a portion of the thinned die includes the at least one deep well.

### Claim 15 (depends on 1)

The printed circuit module of claim 1 wherein the electrical resistivity of the outer protective layer ranges from about 1012 Ohm-cm to around 1016 Ohm-cm.

### Claim 16 (depends on 1)

The printed circuit module of claim 1 wherein the electrical resistivity of the outer protective layer ranges from around about 106 Ohm-cm to around about 1012 Ohm-cm.

### Claim 17 (depends on 1)

The printed circuit module of claim 1 further including a mid-protective layer that is disposed between the thinned die and the outer protective layer.

### Claim 18 (depends on 17)

The printed circuit module of claim 17 wherein the mid-protective layer is made of ceramic material and the outer protective layer is made of a polymer.

### Claim 19 (depends on 1)

The printed circuit module of claim 1 wherein the thinned die is a bulk-complementary metal oxide semiconductor (CMOS) type die.