# US 10,121,716 B2 · Silicon package for embedded semiconductor chip and power converter

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,121,716 B2
- Document ID: US10121716B2
- Status: Granted
- Kind: B2
- Application number: 15/634,232
- Filed: 2017-06-27
- Published: 2017-10-19
- Granted: 2018-11-06
- Earliest claimed: 2014-11-06
- Assignees: Texas Instruments Incorporated
- Applicants: Texas Instruments Incorporated
- Inventors: Osvaldo Jorge Lopez; Jonathan Almeria Noquil; Tom Grebs; Simon John Molloy
- Web page: https://patentgrep.com/patent/US10121716B2

## CPC

- H10W 70/698: Semiconductor materials that are electrically insulating, e.g. undoped silicon
- H10W 40/253: {Semiconductors}
- H10W 70/05: of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04)
- H10W 70/68: Shapes or dispositions thereof
- H10W 72/0198: {batch processes}
- H10W 72/073: {of die-attach connectors}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H10W 70/682: {comprising holes having chips therein}
- H10W 72/07352: {changes in structures or sizes}
- H10W 72/325: {Die-attach connectors having a filler embedded in a matrix}
- H10W 72/327: {Multiple die-attach connectors having different sizes}
- H10W 72/352: {comprising metals or metalloids, e.g. solders}
- H10W 72/354: {comprising polymers}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/944: {Dispositions of multiple bond pads}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

## Claims

### Claim 1

A method for fabricating a packaged transistor device comprising:
providing a wafer of low-grade silicon (l-g-Si) including a plurality of slab sites, each site configured into ridges with a top in a first plane, the ridges framing a depression including a recessed central area in a second plane spaced from the first plane by a depth;
forming a second insulating layer on the second silicon surface, covering all slab sites;
depositing at least one layer of metal onto the second insulating layer;
patterning the metal layer at each slab site, forming in the central site portion a plurality of pads matching the terminals of a transistor, and retaining the metal on the ridges as terminals;
depositing a layer of passivation material onto the patterned metal layer, covering all slab sites;
removing, at each slab site, the passivation layer from the terminals on the ridges and from the pads in the central portion, to expose the underlying metal, while leaving un-removed the passivation material over the slopes and between the pads;
providing a plurality of chips including transistors having terminals on the first and the second chip side; and
attaching the terminals of first chip sides to respective pads in the central portion of each slab site so that the terminals of the opposite second chip side are co-planar with the metal layer of the ridges framing each central portion, whereby the slab serves as the package of the transistor device.

### Claim 2 (depends on 1)

The method of claim 1 wherein the low-grade silicon (l-g-Si) of the wafer is selected from a group including, but not limited to, reclaimed silicon, unrefined silicon, undoped silicon, polycrystalline silicon, intrinsic polycrystalline silicon, lowly doped n-type polycrystalline silicon, and lowly doped p-type polycrystalline silicon.

### Claim 3 (depends on 1)

The method of claim 1 wherein the process of attaching uses an adhesive conductive polymeric compound.

### Claim 4 (depends on 1)

The method of claim 1 further including the process of sawing the l-g-Si wafer to singulate a plurality of slabs, each slab packaging a discrete transistor device.

### Claim 5 (depends on 4)

The method of claim 4 wherein the sawing process is performed by a laser technique.

### Claim 6 (depends on 1)

The method of claim 1 wherein the layers of metal include a layer each of titanium, titanium nitride, and aluminum.

### Claim 7 (depends on 1)

The method of claim 1 further including the process of depositing a layer of nickel followed by an outermost layer of gold on the aluminum layer.

### Claim 8 (depends on 1)

The method of claim 1 further including the process of attaching a heat sink to the device surface opposite the attached chip.

### Claim 9

A method for fabricating a packaged transistor device comprising:
providing a wafer of low-grade low-resistivity silicon (l-g-Si) including a plurality of slab sites, each site configured into ridges with a top in a first plane, the ridges framing a depression including a recessed central area in a second plane spaced from the first plane by a depth;
forming a second insulating layer on the second silicon surface, covering all slab sites;
removing, at each slab site, the second insulating layer from selected pads matching certain terminals of a transistor, to expose the underlying low-resistivity l-g-Si;
depositing at least one layer of metal onto the second insulating layer and the pads of exposed l-g-Si, covering all slab sites;
pattering the metal layer at each slab site, forming in the central site portion a plurality of pads matching the terminals of a transistor, including the power terminals, and retaining the metal on the frames as terminals;
depositing a layer of passivation onto the patterned metal layer, covering all slab sites;
removing, at each slab site, the passivation layer from the terminals on the ridges and from the pads in the central portion, to expose the underlying metal, while leaving un-removed the passivation material over the slopes and between the pads;
providing a plurality of chips including transistors having terminals on the first and the second chip side, the terminals of the first chip sides including a sub-set of power terminals; and
attaching the terminals of first chip sides to respective pads in the central portion of each slab site, the power terminals to the pads of exposed l-g-Si, so that the terminals of the opposite second chip side are co-planar with the metal layer of the ridges framing each central portion, whereby the slab serves as the package of the transistor device.

### Claim 10 (depends on 9)

The method of claim 9 wherein the low-grade silicon (l-g-Si) of the wafer is selected from a group including, but not limited to, reclaimed low-resistivity silicon, unrefined low-resistivity silicon, polycrystalline low-resistivity silicon, heavily doped n-type polycrystalline silicon, and heavily doped p-type polycrystalline silicon.

### Claim 11 (depends on 9)

The method of claim 9 further including the process of sawing the l-g-Si wafer to singulate a plurality of slabs, each slab packaging a discrete electronic system.