# US 10,121,715 B2 · Jig for fabricating semiconductor device

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- Number: US 10,121,715 B2
- Document ID: US10121715B2
- Status: Granted
- Kind: B2
- Application number: 15/150,641
- Filed: 2016-05-10
- Published: 2016-12-22
- Granted: 2018-11-06
- Earliest claimed: 2015-06-18
- Assignees: Fuji Electric Co., Ltd.
- Applicants: Fuji Electric Co., Ltd.
- Inventors: Yo Sakamoto
- Web page: https://patentgrep.com/patent/US10121715B2

## CPC

- H10W 76/153: having interconnections in passages through the insulating or insulated base
- H05K 3/306: with lead-in-hole components (H05K3/32 takes precedence)
- H10W 42/121: {protecting against mechanical damage (H10W76/00, H10W74/00 take precedence)}
- H10W 70/611: {for connecting multiple chips together}
- H10W 70/635: {Through-vias}
- H10W 70/65: Shapes or dispositions of interconnections
- H10W 72/071: {Connecting or disconnecting}
- H10W 90/00: Package configurations
- H05K 3/3447: Lead-in-hole components
- H05K 2201/2036: Permanent spacer or stand-off in a printed circuit or printed circuit assembly
- H05K 2203/167: Using mechanical means for positioning, alignment or registration, e.g. using rod-in-hole alignment
- H10W 70/60: Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40)
- H10W 70/681: {comprising holes not having chips therein, e.g. for outgassing, underfilling or bond wire passage}
- H10W 72/884: {Die-attach connectors and bond wires}
- H10W 90/291: {characterised by containers, encapsulations, or other housings for the stacked chips}
- H10W 90/701: {characterised by the relative positions of pads or connectors relative to package parts}
- H10W 90/734: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS

## Abstract

A semiconductor device fabrication method, including preparing a case having a plurality of connection terminals, and fitting a jig onto the case to protect the connection terminals, tips of the connection terminals protruding from the jig. The method further includes fitting a printed circuit board on the tips of the connection terminals protruding from the jig.

## Claims

### Claim 1

A jig for fabricating a semiconductor device that includes
a case housing a semiconductor element, and
connection terminals, formed on the case, that are electrically connected to main electrodes of the semiconductor element,
the jig comprising:
a first plate portion and a second plate portion, one of the first and second plate portions having a plurality of holding portions formed therein, and
a fixing portion fixing the first and second plate portions, so that the connection terminals are held in and protected by the holding portions, tips of the connection terminals being protrusible from the jig.

### Claim 2 (depends on 1)

The jig according to claim 1, wherein the holding portions are grooves.

### Claim 3 (depends on 1)

The jig according to claim 1, wherein the holding portions are elastic members.

### Claim 4 (depends on 1)

The jig according to claim 1, wherein
the semiconductor device further includes a printed circuit board having a plurality of acceptance portions, and
the holding portion has a height above which the tips of the connection terminals protruding from the jig are fitted in the acceptance portions.

### Claim 5

A semiconductor device, comprising
a case housing a semiconductor element that has a plurality of main electrodes;
a plurality of connection terminals, formed on the case and electrically connected to the main electrodes of the semiconductor element;
a printed circuit board electrically connected to the connection terminals, the printed circuit board being formed using a jig that holds the connection terminals and being thus formed on tips of the connection terminals protruding from the jig; and
a plurality of guide pins disposed on peripheral edge portions of the case.

### Claim 6 (depends on 5)

The semiconductor device according to claim 5, wherein the connection terminals are disposed in a line with the guide pins.