# US 10,121,713 B1 · In-kerf test structure and testing method for a memory array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,713 B1 - Document ID: US10121713B1 - Status: Granted - Kind: B1 - Application number: 15/589,126 - Filed: 2017-05-08 - Published: 2018-11-08 - Granted: 2018-11-06 - Earliest claimed: 2017-05-08 - Assignees: Globalfoundries Inc. - Applicants: Globalfoundries Inc. - Inventors: Bipul C. Paul; Hajime Terazawa; Joseph Versaggi - Web page: https://patentgrep.com/patent/US10121713B1 ## CPC - H10P 74/277: {Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers} - H10P 74/207: {Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics} - G01R 31/00: Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - H10B 10/18: {Peripheral circuit regions} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) - H10B: ELECTRONIC MEMORY DEVICES ## Abstract Disclosed are an in-kerf test structure and testing method for testing an on-chip device. The structure includes at least one test component with at least one test device and adjoining dummy devices connected to the test device. Each adjoining dummy device has proximal node(s) directly connected to a test device and distal node(s) that are not directly connected to a test device. The nodes of each test device and the distal nodes of each adjoining dummy device are connected to input/output pads. During testing the input/output pads are used to bias the nodes of a selected test device as well as the distal node(s) of any adjoining dummy device. By biasing the distal node(s) of an adjoining dummy device, random accumulation of potential thereon is avoided and current contributions from the adjoining dummy device(s) to a current measurement taken from the selected test device can be accurately determined. ## Claims ### Claim 1 A semiconductor structure comprising: a semiconductor wafer; and, a test structure on the semiconductor wafer, wherein the test structure comprises: a test component comprising: at least one test device comprising first nodes; and adjoining dummy devices, wherein each adjoining dummy device comprises second nodes comprising at least one proximal second node that is directly connected to a first node of the at least one test device and at least one distal second node; and input/output pads that are electrically connected to the first nodes of the at least one test device and to the at least one distal second node of each of the adjoining dummy devices, wherein the input/output pads allow biasing of the first nodes of the at least one test device and the at least one distal second node of each of the adjoining dummy devices during testing, wherein the input/output pads comprise at least two shared input/output pads, wherein the shared input/output pads comprise a pair of shared input/output pads to allow biasing of all distal second nodes of all the adjoining dummy devices, and wherein the test structure is within a kerf region of the semiconductor wafer. ### Claim 2 (depends on 1) The semiconductor structure of claim 1, wherein biasing distal second nodes of the adjoining dummy devices prevents random accumulation of potential on the distal second nodes. ### Claim 3 (depends on 1) The semiconductor structure of claim 1, wherein each shared input/output pad is electrically connected to a group of nodes having common bias conditions for all tests. ### Claim 4 A semiconductor structure comprising: a semiconductor wafer; and, a test structure on the semiconductor wafer, wherein the test structure comprises: a test component for characterization of parameters of three different types of field effect transistors, respectively, within a static random access memory cell of a static random access memory array, wherein the test component comprises three sections including a first section, a second section and a third section and wherein each of the three sections comprises: multiple test devices within a static random access memory cell, wherein each test device comprises first nodes; and adjoining dummy devices, wherein each adjoining dummy device comprises second nodes, comprising a proximal second node that is directly connected to a first node of a test device of the multiple test devices and at least one distal second node, wherein the test devices in the first section comprise pass gate field effect transistors, the test devices in the second section comprise pull up field effect transistors, and the test devices in the third section comprise pull down field effect transistors; and input/output pads that are electrically connected to the first nodes of each test device in each section and to the at least one distal second node of each adjoining dummy device in each section, wherein the input/output pads allow biasing of the first nodes of a selected test device of the test devices and each distal second node of any adjoining dummy devices during testing, wherein the input/output pads comprise at least two shared input/output pads, and wherein the shared input/output pads comprise a pair of shared input/output pads to allow biasing of all distal second nodes of all the adjoining dummy devices. ### Claim 5 (depends on 4) The semiconductor structure of claim 4, wherein biasing distal second nodes of the adjoining dummy devices prevents random accumulation of potential on the distal second nodes. ### Claim 6 (depends on 4) The semiconductor structure of claim 4, wherein each shared input/output pad is electrically connected to a group of nodes having common bias conditions for all tests. ### Claim 7 (depends on 4) The semiconductor structure of claim 4, the test structure further comprising a second test component for characterization of parameters of the static random access memory cell and a third test component for characterization of static random access memory cell leakage.