# US 10,121,706 B2 · Semiconductor structure including two-dimensional and three-dimensional bonding materials

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- Number: US 10,121,706 B2
- Document ID: US10121706B2
- Status: Granted
- Kind: B2
- Application number: 15/361,809
- Filed: 2016-11-28
- Published: 2018-05-31
- Granted: 2018-11-06
- Earliest claimed: 2016-11-28
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Rinus T. P. Lee; Bharat V. Krishnan; Hui Zang; Matthew W. Stoker
- Web page: https://patentgrep.com/patent/US10121706B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6212: {having fin-shaped semiconductor bodies having non-rectangular cross-sections}
- H10D 62/115: {Dielectric isolations, e.g. air gaps}
- H10D 62/53: the imperfections being within the semiconductor body
- H10D 84/0167: {Manufacturing their channels}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/853: {comprising FinFETs}
- H10P 14/6548: {by forming intermediate materials, e.g. capping layers or diffusion barriers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/0158: {the components including FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

One aspect of the disclosure is directed to a method of forming a semiconductor structure. The method including: removing each fin in a set of fins from between insulator pillars to expose a portion of a substrate between each insulator pillar, the substrate having a first device region and a second device region; forming a first material over the exposed portions of the substrate between each insulator pillar, the first material including a two-dimensional material; forming a second material over the first material in the first device region, the second material including a first three-dimensional bonding material; and forming a third material over the exposed first material in the second device region, the third material including a second three-dimensional bonding material.

## Claims

### Claim 1

A semiconductor structure comprising:
a set of fins over a substrate, each fin in the set of fins comprising a three-dimensional bonding material;
an insulator pillar on the substrate between each fin in the set of fins; and
a two dimensional material layer positioned directly between the three-dimensional bonding material and the substrate, and between the three-dimensional bonding material and each insulator pillar.

### Claim 2 (depends on 1)

The semiconductor structure of claim 1, wherein the two-dimensional material includes at least one of: molybdenum disulfide, tungsten diselenide, boron phosphide, hafnium diselenide, black phosphorus, phosporene, germanane, hafnium disulphide, or graphene.

### Claim 3 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor structure is a n-type field effect transistor, and
wherein the three-dimensional bonding material includes at least one of: silicon, silicon germanium, germanium, germanium tin, indium, gallium, arsenide, nitride, or combinations thereof.

### Claim 4 (depends on 1)

The semiconductor structure of claim 1, wherein the semiconductor structure is a p-type field effect transistor, and
wherein the three-dimensional bonding material includes at least one of: silicon, silicon germanium, germanium, and germanium tin, indium, antimonide, or combinations thereof.

### Claim 5 (depends on 1)

The semiconductor structure of claim 1, wherein the three-dimensional bonding material includes a material having a lattice that does not match a lattice of the substrate.

### Claim 6

A semiconductor structure comprising:
a first device region and a second device region over a substrate;
wherein the first device region includes:
a first set of fins over the substrate, each fin in the first set of fins being separated from an adjacent fin in the first set of fins by an insulator pillar in a set of insulator pillars, and each fin in the first set of fins comprising a first three-dimensional bonding material, and
wherein the second device region includes:
a second set of fins on the substrate, each fin in the second set of fins being separated from an adjacent fin in the second set of fins by another insulator pillar in the set of insulator pillars, and each fin in the second set of fins comprising a second three-dimensional bonding material; and
a two-dimensional material layer directly between the substrate and the first three-dimensional bonding material, between the insulator pillar and the first three-dimensional bonding material, between the substrate and the second three-dimensional bonding material, and between the another insulator pillar and the second three-dimensional bonding material.

### Claim 7 (depends on 6)

The semiconductor structure of claim 6, wherein the two-dimensional material includes at least one of: molybdenum disulfide, tungsten diselenide, boron phosphide, hafnium diselenide, black phosphorus, phosporene, germanane, hafnium disulphide, or graphene.

### Claim 8 (depends on 6)

The semiconductor structure of claim 6, wherein the first device region includes a n-type field effect transistor (nFET) and the second device region includes an p-type field effect transistor (pFET), and
wherein the first three-dimensional bonding material includes at least one of: silicon, silicon germanium, germanium, germanium tin, indium, gallium, arsenide, nitride, or combinations thereof, and the second three-dimensional bonding material includes at least one of: silicon, silicon germanium, germanium, and germanium tin, indium, antimonide, or combinations thereof.

### Claim 9 (depends on 6)

The semiconductor structure of claim 6, wherein the first and second three-dimensional bonding materials each include a material having a lattice that does not match a lattice of the substrate.