# US 10,121,704 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,121,704 B2
- Document ID: US10121704B2
- Status: Granted
- Kind: B2
- Application number: 15/861,692
- Filed: 2018-01-04
- Published: 2018-05-24
- Granted: 2018-11-06
- Earliest claimed: 2016-11-23
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: En-Chiuan Liou; Yu-Cheng Tung
- Web page: https://patentgrep.com/patent/US10121704B2

## CPC

- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0153: {using gate cut processes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/0188: {Manufacturing their isolation regions}
- H10D 84/0135: {Manufacturing their gate conductors}
- H10D 86/011: {comprising FinFETs}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device includes a semiconductor substrate, a shallow trench isolation structure, gate electrodes, and a gate isolation structure. The semiconductor substrate includes fin structures, and each of the fin structures is elongated in a first direction. The shallow trench isolation structure is disposed on the semiconductor substrate and disposed between the fin structures. The gate electrodes are disposed on the semiconductor substrate and the shallow trench isolation structure. Each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures. The gate isolation structure is disposed between two adjacent gate electrodes in the second direction, and a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure. The gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.

## Claims

### Claim 1

A manufacturing method of a semiconductor device, comprising:
providing a semiconductor substrate, wherein the semiconductor substrate comprises a plurality of fin structures, and each of the fin structures is elongated in a first direction;
forming a shallow trench isolation structure on the semiconductor substrate, wherein the shallow trench isolation structure is located between the fin structures;
forming a plurality of gate structures on the semiconductor substrate and the shallow trench isolation structure, wherein each of the gate structures is elongated in a second direction and disposed straddling at least one of the fin structures; and
forming a gate isolation structure cutting at least one of the gate structures into two gate electrodes, wherein a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure, and the gate isolation structure is aligned with the two gate electrodes in the second direction.

### Claim 2 (depends on 1)

The manufacturing method of claim 1, wherein wherein each of the gate electrodes comprises:
a gate material layer; and
a capping layer disposed on the gate material layer, wherein a top surface of the gate isolation structure is coplanar with a top surface of the capping layer.

### Claim 3 (depends on 1)

The manufacturing method of claim 1, wherein an edge of the gate isolation structure is aligned with edges of the two gate electrodes in the second direction.

### Claim 4 (depends on 1)

The manufacturing method of claim 1, wherein the step of forming the gate isolation structure comprises:
forming a recess penetrating the gate structure corresponding to the gate isolation structure, wherein the recess is formed on one of the fin structures, and a part of the fin structure is removed by the step of forming the recess; and
filling the recess with an insulation material.

### Claim 5 (depends on 4)

The manufacturing method of claim 4, wherein the recess comprises:
a first part; and
a second part located under the first part, wherein the second part is lower than the top surface of the shallow trench isolation structure.

### Claim 6 (depends on 5)

The manufacturing method of claim 5, wherein a width of the first part is larger than a width of the second part.

### Claim 7 (depends on 5)

The manufacturing method of claim 5, wherein a bottom surface of the second part is higher than a bottom surface of the shallow trench isolation structure.

### Claim 8 (depends on 7)

The manufacturing method of claim 7, wherein the part of the fin structure is removed by the step of forming the recess for forming a recessed part in the fin structure, the gate isolation structure is formed on the recessed part of the fin structure, and the recessed part of the fin structure is formed corresponding to the recess.

### Claim 9

A semiconductor device, comprising:
a semiconductor substrate comprising a plurality of fin structures, wherein each of the fin structures is elongated in a first direction;
a shallow trench isolation structure disposed on the semiconductor substrate and disposed between the fin structures;
a plurality of gate electrodes disposed on the semiconductor substrate and the shallow trench isolation structure, wherein each of the gate electrodes is elongated in a second direction and disposed straddling at least one of the fin structures; and
a gate isolation structure disposed between two of the gate electrodes adjacent with one another in the second direction, wherein a bottom surface of the gate isolation structure is lower than a top surface of the shallow trench isolation structure, and the gate isolation structure is aligned with the gate electrodes adjacent to the gate isolation structure in the second direction.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein each of the gate electrodes comprises:
a gate material layer; and
a capping layer disposed on the gate material layer, wherein a top surface of the gate isolation structure is coplanar with a top surface of the capping layer.

### Claim 11 (depends on 9)

The semiconductor device of claim 9, wherein an edge of the gate isolation structure is aligned with edges of the gate electrodes adjacent to the gate isolation structure in the second direction.

### Claim 12 (depends on 9)

The semiconductor device of claim 9, wherein at least one of the fin structures comprises:
two sub fin structures disposed adjacent to each other in the first direction, wherein the gate isolation structure is disposed between the two sub fin structures in the first direction.

### Claim 13 (depends on 12)

The semiconductor device of claim 12, wherein the fin structure further comprises:
a recessed part disposed between the two sub fin structures in the first direction, wherein the gate isolation structure is disposed on the recessed part of the fin structure.

### Claim 14 (depends on 13)

The semiconductor device of claim 13, wherein a top surface of the recessed part is lower than the top surface of the shallow trench isolation structure and higher than a bottom surface of the shallow trench isolation structure.

### Claim 15 (depends on 9)

The semiconductor device of claim 9, wherein the gate isolation structure comprises:
a first section; and
a second section disposed under the first section, wherein the second section is lower than the top surface of the shallow trench isolation structure.

### Claim 16 (depends on 15)

The semiconductor device of claim 15, wherein a bottom surface of the second section is higher than a bottom surface of the shallow trench isolation structure.

### Claim 17 (depends on 15)

The semiconductor device of claim 15, wherein a part of the first section is disposed on the shallow trench isolation structure.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein a width of the first section is larger than a width of the second section.