# US 10,121,703 B2 · Contact structure and extension formation for III-V nFET

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- Number: US 10,121,703 B2
- Document ID: US10121703B2
- Status: Granted
- Kind: B2
- Application number: 15/789,972
- Filed: 2017-10-21
- Published: 2018-03-01
- Granted: 2018-11-06
- Earliest claimed: 2015-05-21
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Veeraraghavan S. Basker; Alexander Reznicek
- Web page: https://patentgrep.com/patent/US10121703B2

## CPC

- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/01: Manufacture or treatment
- H10D 30/021: {of FETs having insulated gates [IGFET]}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates}
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 30/751: {having composition variations in the channel regions}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/113: {Isolations within a component, i.e. internal isolations}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/82: Heterojunctions
- H10D 62/85: being Group III-V materials, e.g. GaAs
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 84/0128: {Manufacturing their channels}
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0193: {the components including FinFETs}
- H10D 84/02: characterised by using material-based technologies
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/05: using Group III-V technology
- H10D 84/08: using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies
- H10D 84/834: {comprising FinFETs}
- H10D 84/853: {comprising FinFETs}
- H10D 86/011: {comprising FinFETs}
- H10D 86/215: {comprising FinFETs}
- H10P 14/2905: {Silicon, silicon germanium or germanium}
- H10P 14/2924: {Structures}
- H10P 14/3218: {Phosphides}
- H10P 14/3221: {Arsenides}
- H10P 14/3248: {consisting of two layers}
- H10P 14/3411: {Silicon, silicon germanium or germanium}
- H10P 14/3421: {Arsenides}
- H10P 14/3802: {Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth}
- H10P 14/3822: {Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 30/28: characterised by an annealing step, e.g. for activation of dopants
- H10P 32/14: within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
- H10P 32/174: {being Group III-V material}
- H10P 95/408: {of Group III-V semiconductors, e.g. to render them semi-insulating}
- H10P 95/90: Thermal treatments, e.g. annealing or sintering
- H10P 95/904: {of Group III-V semiconductors}
- H10P 14/24: using chemical vapour deposition [CVD]
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

FinFET devices including III-V fin structures and silicon-based source/drain regions are formed on a semiconductor substrate. Silicon is diffused into the III-V fin structures to form n-type junctions. Leakage through the substrate is addressed by forming p-n junctions adjoining the source/drain regions and isolating the III-V fin structures under the channel regions.

## Claims

### Claim 1

A method of fabricating fin-type field-effect transistors, comprising:
obtaining a semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers;
epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
forming n-type source/drain regions from the silicon-based semiconductor layer,
wherein epitaxially growing the silicon-based semiconductor layer further includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and having a top surface entirely beneath the portions of the III-V fin structures comprising each column and a second, undoped silicon layer on the first, p-type silicon layer, the n-type source/drain regions being formed from the second, undoped silicon layer subsequent to the first annealing process, and
further wherein forming n-type source/drain regions from the silicon-based semiconductor layer includes implanting dopant ions within the second, undoped silicon layer and subjecting the columns and the silicon-based semiconductor layer to a second annealing process subsequent to the first annealing process, thereby causing the second, undoped silicon layer to recrystallize following ion implantation.

### Claim 2 (depends on 1)

The method of claim 1, further including:
growing a III-V semi-isolating layer on the first III-V blanket layer,
forming the second III-V blanket layer on the III-V semi-isolating layer, and
forming the plurality of recess through the III-V semi-isolating layer, wherein the III-V base of each column includes a portion of the semi-isolating III-V layer adjoining one of the portions of the III-V fin structures.

### Claim 3 (depends on 2)

The method of claim 2, further including forming local isolation regions on the semi-isolating layer of III-V material.

### Claim 4 (depends on 1)

The method of claim 1, wherein the semiconductor substrate consists essentially of mono-crystalline silicon.

### Claim 5 (depends on 4)

The method of claim 4, wherein epitaxially growing the silicon-based semiconductor layer includes using silane as a source gas.

### Claim 6 (depends on 1)

The method of claim 1, wherein forming the n-type source/drain regions includes implanting the silicon-based semiconductor layer with arsenic or phosphorus ions subsequent to the first annealing process and followed by a second annealing process causing recrystallization of the silicon-based semiconductor layer.

### Claim 7 (depends on 6)

The method of claim 6, wherein epitaxially growing the silicon-based semiconductor layer includes using silane as a source gas.

### Claim 8 (depends on 7)

The method of claim 7, wherein the III-V fin structures comprise arsenic, and further causing arsenic from the III-V fin structures to be diffused into the silicon-based semiconductor layer during the first annealing process.

### Claim 9

A method of fabricating fin-type field-effect transistors, comprising:
obtaining a semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portions of the III-V fin structures comprising the columns including top surfaces;
epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
forming n-type source/drain regions from the silicon-based semiconductor layer,
wherein epitaxially growing the silicon-based semiconductor layer further includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and a second, undoped silicon layer on the first, p-type silicon layer, the second, undoped silicon layer being epitaxially grown to or above the top surfaces of the portions of the III-V fin structures, the n-type source/drain regions being formed from the second, undoped silicon layer subsequent to the first annealing process, and
further wherein forming n-type source/drain regions from the silicon-based semiconductor layer includes implanting dopant ions within the second, undoped silicon layer and subjecting the columns and the silicon-based semiconductor layer to a second annealing process subsequent to the first annealing process, thereby causing the second, undoped silicon layer to recrystallize following ion implantation.

### Claim 10

A method of fabricating fin-type field-effect transistors, comprising:
obtaining a semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
growing a III-V semi-isolating layer on the first III-V blanket layer;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer and on the III-V semi-isolating layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses through the first III-V blanket layer, the III-V semi-isolating layer, and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of the semi-isolating III-V layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portion of the semi-isolating III-V layer of each column adjoining the portion of the III-V fin structure of each column;
forming local isolation regions of III-V material on the semi-isolating III-V layer;
epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
forming n-type source/drain regions from the silicon-based semiconductor layer.

### Claim 11

A method of fabricating fin-type field-effect transistors, comprising:
obtaining a semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate, wherein epitaxially growing the first III-V blanket layer on the semiconductor substrate further includes growing, in order, gallium arsenide, indium phosphide and indium gallium arsenide on the semiconductor substrate, the gallium arsenide being formed directly on a top surface of the semiconductor substrate;
growing a III-V semi-isolating layer on the first III-V blanket layer;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer and on the III-V semi-isolating layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses through the first III-V blanket layer, the III-V semi-isolating layer, and the III-V fin structures down to the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures, one of the plurality of gate structures, and one of the dielectric spacers, the portion of the semi-isolating III-V layer of each column adjoining the portion of the III-V fin structure of each column;
epitaxially growing a silicon-based semiconductor layer on an exposed surface of the semiconductor substrate and within the recesses such that a portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the silicon-based semiconductor layer into the III-V fin structures to form n-type junctions, and
forming n-type source/drain regions from the silicon-based semiconductor layer.

### Claim 12 (depends on 11)

The method of claim 11, wherein the semi-isolating layer is formed from InAlAs and the III-V fin structures are formed from In0.53Ga0.47As.

### Claim 13

A method of fabricating fin-type field-effect transistors, comprising:
obtaining a silicon-based semiconductor substrate;
epitaxially growing a first III-V blanket layer directly on a top surface of the semiconductor substrate;
epitaxially growing a second III-V blanket layer above the first III-V blanket layer;
forming a plurality of III-V fin structures from the second III-V blanket layer;
forming a plurality of gate structures on the III-V fin structures;
forming dielectric spacers on the gate structures;
forming a plurality of recesses by etching through the first III-V blanket layer and the III-V fin structures down to the semiconductor substrate and exposing a top surface of the semiconductor substrate, thereby forming a plurality of columns extending upwardly from the semiconductor substrate, each of the columns including a III-V base formed from the first III-V blanket layer, a portion of one of the III-V fin structures above the III-V base, one of the plurality of gate structures, and one of the dielectric spacers;
epitaxially growing a silicon-based semiconductor layer on the exposed top surface of the semiconductor substrate and within the recesses such that an undoped portion of the silicon-based semiconductor layer adjoins the portions of the III-V fin structures comprising each of the columns;
subjecting the columns and the silicon-based semiconductor layer to a first annealing process, thereby causing diffusion of silicon from the undoped portion of the silicon-based semiconductor layer into the III-V fin structures and diffusion of a group V element from the III-V fin structures into the undoped portion of the silicon-based semiconductor layer to form n-type junctions, and
introducing dopant ions to the undoped portion of the silicon-based semiconductor layer to form n-type source/drain regions adjoining the n-type junctions from the undoped portion of the silicon-based semiconductor layer.

### Claim 14 (depends on 13)

The method of claim 13, wherein the step of epitaxially growing the silicon-based semiconductor layer includes epitaxially growing a first, p-type silicon layer on the semiconductor substrate and a second, undoped silicon layer on the first, p-type silicon layer, the n-type source/drain regions being formed from the second, undoped silicon layer subsequent to the first annealing process.

### Claim 15 (depends on 14)

The method of claim 14, wherein the step of forming n-type source/drain regions from the silicon-based semiconductor layer includes implanting n-type dopant ions within the second, undoped silicon layer and subjecting the columns and silicon-based semiconductor layer to a second annealing process subsequent to the first annealing process, thereby causing the second, undoped silicon layer to recrystallize following ion implantation and forming pn junctions within the silicon-based semiconductor layer.

### Claim 16 (depends on 15)

The method of claim 15, wherein the first, p-type silicon layer has a top surface entirely beneath the portions of the III-V fin structures comprising each column.

### Claim 17 (depends on 15)

The method of claim 15, wherein the portions of the III-V fin structures comprising the columns include top surfaces, and further wherein epitaxially growing the silicon-based semiconductor layer further includes epitaxially growing the second, undoped silicon layer to or above the top surfaces of the portions of the III-V fin structures.

### Claim 18 (depends on 13)

The method of claim 13, wherein the III-V fin structures are comprised of a III-V compound including arsenic, and further wherein causing diffusion of a group V element from the III-V fin structures into the undoped portion of the silicon-based semiconductor layer using the first annealing process further includes causing arsenic from the III-V fin structures to be diffused into the silicon-based semiconductor layer to form the n-type junctions.