# US 10,121,702 B1 · Methods, apparatus and system for forming source/drain contacts using early trench silicide cut

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- Number: US 10,121,702 B1
- Document ID: US10121702B1
- Status: Granted
- Kind: B1
- Application number: 15/638,087
- Filed: 2017-06-29
- Granted: 2018-11-06
- Earliest claimed: 2017-06-29
- Assignees: Globalfoundries Inc.
- Applicants: Globalfoundries Inc.
- Inventors: Chanro Park; Min Gyu Sung; Ruilong Xie; Puneet H. Suvarna
- Web page: https://patentgrep.com/patent/US10121702B1

## CPC

- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10D 30/024: {of fin field-effect transistors [FinFET]}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 30/6219: {characterised by the source or drain electrodes}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0151: {Manufacturing their isolation regions}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/834: {comprising FinFETs}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10D 84/013: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

At least one method, apparatus and system disclosed herein involves performing an early-process of source/drain (S/D) contact cut and S/D contact etch steps for manufacturing a finFET device. A gate structure, a source structure, and a drain structure of a transistor are formed. The gate structure comprises a dummy gate region, a gate spacer, and a liner. A source/drain (S/D) contact cut process is performed. An S/D contact etch process is performed. A replacement metal gate (RMG) process is performed subsequent to performing the S/D contact etch process. An S/D contact metallization process is performed.

## Claims

### Claim 1

A method, comprising:
forming a gate structure, a source structure, and a drain structure of a transistor, wherein said gate structure comprises a dummy gate region, a gate spacer, and a liner;
performing a source/drain (S/D) contact cut process comprised of performing a TS etch process for forming a non-TS trench;
depositing a dielectric layer into said non-TS trench;
performing a S/D contact etch process;
performing a replacement metal gate (RMG) process subsequent to performing said S/D contact etch process; and
performing an S/D contact metallization process.

### Claim 2 (depends on 1)

The method of claim 1, wherein performing said S/D contact cut process comprises performing a trench silicide (TS) cut process comprising:
determining a non-TS location of said transistor; and
forming a non-TS lithography stack.

### Claim 3 (depends on 2)

The method of claim 2, wherein forming said non-TS lithography stack comprises:
forming an amorphous-carbon (a-C) layer;
forming an anti-reflective coat (ARC) layer over said a-C layer; and
forming a photoresist layer above said a-C layer, wherein said photoresist layer is formed only in regions outside said non-TS location.

### Claim 4 (depends on 3)

The method of claim 3, wherein performing said TS etch process for forming a non-TS trench comprises performing a reactive ion etch (RIE) process for removing a portion of said a-C layer and a portion of said ARC layer in the non-TS location.

### Claim 5 (depends on 1)

The method of claim 1, wherein depositing a dielectric layer into said non-TS trench, further comprises depositing at least one of a SiN material, a SiCO material, a SiOCN material, or a SiBCN material.

### Claim 6 (depends on 1)

The method of claim 1, wherein performing said RMG process comprises:
performing a poly open CMP (POC) process for exposing said dummy gate region;
performing a poly-etch process for removing a poly-silicon material from said dummy gate region, thereby creating a first void in place of said dummy gate region;
depositing a gate metal into said first void; and
performing a metal gate CMP process for polishing said gate metal to a predetermined height.

### Claim 7 (depends on 6)

The method of claim 6, further comprising:
depositing an inter-layer dielectric (ILD) material outside said non-TS location prior to performing said RMG process;
performing an ILD removal process for removing said ILD material outside said non-TS location, thereby creating a second void between a plurality of gate features outside said non-TS location; and
removing said liner from horizontal areas and over a first EPI formation of said source structure and a second EPI formation of said drain structure.

### Claim 8 (depends on 6)

The method of claim 6, further comprising:
recessing said a gate metal to depth ranging from about 10 nm to 60 nm, for forming a second void in place of said dummy gate region;
depositing a SiN dielectric material in said second void;
performing a SiN CMP process for polishing said SiN dielectric material to expose a SiO2 dielectric material to form a self-aligned contact (SAC) cap.

### Claim 9 (depends on 1)

The method of claim 1, wherein performing an S/D contact metallization process comprises depositing a metal material into regions outside said non-TS location between a plurality of gate structures.

### Claim 10 (depends on 1)

The method of claim 1, further comprising performing a chemical mechanical polishing process to substantially remove the dielectric layer located outside said non-TS trench.

### Claim 11

A method, comprising:
forming a plurality of gate structures, a plurality of source structures, and a plurality of drain structures of a transistor, wherein each of said gate structures comprises a dummy gate region, a gate spacer, and a liner;
determining a non-TS region of said transistor;
forming a non-TS lithography stack outside said non-TS region;
performing a TS etch process subsequent to forming said non-TS lithography stack for forming a non-TS trench between at least a portion of said plurality of gate structures;
performing a replacement metal gate (RMG) process subsequent to performing said TS etch process; and
performing a TS metallization process outside said non-TS location by depositing a metal material into regions outside said non-TS location between at least a portion of said gate structures.

### Claim 12 (depends on 11)

The method of claim 11, wherein performing said non-TS lithography stack comprises:
forming an amorphous-carbon (a-C) layer;
forming an anti-reflective coat (ARC) layer over said a-C layer; and
forming a photoresist layer above said a-C layer, wherein said photoresist layer is formed only in regions outside said non-TS location.

### Claim 13 (depends on 11)

Original) The method of claim 11, wherein performing said TS etch process comprises performing a reactive ion etch (RIE) process for removing a portion of said a-C layer and a portion of said ARC layer in the non-TS location.

### Claim 14 (depends on 11)

The method of claim 11, further comprising:
depositing a dielectric layer into said non-TS trench, wherein said dielectric layer comprises at least one of a SiN material or a SiCO material;
depositing an inter-layer dielectric (ILD) material outside said non-TS location prior to performing said RMG process;
performing an ILD removal process for removing said ILD material outside said non-TS location creating a plurality of voids between a plurality of gate features outside said non-TS location; and
removing said liner from horizontal areas and over an EPI formation of said source and drain structures; and
wherein performing a TS metallization process comprises depositing a metal material into said voids.

### Claim 15

A system, comprising:
a semiconductor device processing system to manufacture a semiconductor device comprising at least one fin field effect transistor (finFET); and
a processing controller operatively coupled to said semiconductor device processing system, said processing controller configured to control an operation of said semiconductor device processing system;
wherein said semiconductor device processing system is adapted to:
form a gate structure, a source structure, and a drain structure of a transistor, wherein said gate structure comprising a dummy gate region, a gate spacer, and a liner;
perform a source/drain (S/D) contact cut process comprised of performing a TS etch process for forming a non-TS trench;
deposit a dielectric layer into said non-TS trench;
perform a S/D contact etch process;
perform a replacement metal gate (RMG) process subsequent to performing said S/D contact etch process; and
perform an S/D contact metallization process.

### Claim 16 (depends on 15)

The system of claim 15, further comprising a design unit configured to generate a first design comprising a definition for a process mask and a definition for forming a transistor, wherein data from said design unit is used by said processing controller to control an operation of said semiconductor device processing system.

### Claim 17 (depends on 15)

The system of claim 15, wherein to perform said source/drain (S/D) contact cut process, said semiconductor device processing system further adapted to:
determine a non-TS location of said transistor; and
form a non-TS lithography stack.

### Claim 18 (depends on 17)

The system of claim 17, wherein to form said non-TS lithography stack, said semiconductor device processing system further adapted to:
form an amorphous-carbon (a-C) layer;
form an anti-reflective coat (ARC) layer over said a-C layer; and
form a photoresist layer above said a-C layer, wherein said photoresist layer is formed only in regions outside said non-TS location.

### Claim 19 (depends on 15)

The system of claim 15, wherein said semiconductor device processing system further adapted to perform the TS etch process for forming the non-TS trench further comprises performing a reactive ion etch (RIE) process for removing a portion of said a-C layer and a portion of said ARC layer in the non-TS location.

### Claim 20 (depends on 15)

The system of claim 15, wherein said semiconductor device processing system further adapted to:
deposit an inter-layer dielectric (ILD) material outside said non-TS location prior to performing said RMG process;
perform ILD removal process for removing said ILD material outside said non-TS location creating a void between a plurality of gate features outside said non-TS location;
remove said liner from horizontal areas and over an EPI formation of said source and drain structures; and
perform a self-aligned contact (SAC) cap deposition process to form a cap over said gate metal.