# US 10,121,701 B2 · Substrate conductor structure and method

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- Number: US 10,121,701 B2
- Document ID: US10121701B2
- Status: Granted
- Kind: B2
- Application number: 15/220,143
- Filed: 2016-07-26
- Published: 2016-11-17
- Granted: 2018-11-06
- Earliest claimed: 2012-06-26
- Assignees: Intel Corporation
- Applicants: Intel Corporation
- Inventors: Harold Ryan Chase; Mihir K. Roy; Mathew J. Manusharow; Mark Hlad
- Web page: https://patentgrep.com/patent/US10121701B2

## CPC

- H10W 20/057: {by selectively depositing, e.g. by using selective CVD or plating}
- H05K 1/0219: {Printed shielding conductors for shielding around or between signal conductors, e.g. coplanar or coaxial printed shielding conductors}
- H05K 1/0222: {for shielding around a single via or around a group of vias, e.g. coaxial vias or vias surrounded by a grounded via fence}
- H05K 3/4602: {characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated}
- H10P 14/46: using a liquid
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
- H10W 40/10: Arrangements for heating
- H10W 42/20: protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
- H10W 70/635: {Through-vias}
- H10W 99/00: Subject matter not provided for in other groups of this subclass
- H05K 2201/09581: Applying an insulating coating on the walls of holes
- H10W 72/252: {comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/877: {Bump connectors and die-attach connectors}
- H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL}
- H10W 90/736: {between a chip and a stacked lead frame, conducting package substrate or heat sink}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H05K: PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of substrates, semiconductor devices and methods are shown that include elongated structures to improve conduction. Elongated structures and methods are also shown that provide electromagnetic isolation to reduce noise in adjacent components.

## Claims

### Claim 1

A method of forming a semiconductor device, comprising:
ablating core material to form a first non-cylindrical hole in the core material, the first non-cylindrical hole comprising a first substantially elongated slot with rounded ends;
situating first conductor material on walls of the first non-cylindrical hole;
using a flash plate step to increase a thickness of the first conductor material on the walls of the first non-cylindrical hole;
filling a void between the walls lined with the first conductor material with a plugging resin;
ablating the plugging resin to form a second non-cylindrical hole all the way through the resin, the second non-cylindrical hole contained within the first non-cylindrical hole, the second non-cylindrical hole comprising a second substantially elongated slot with rounded ends;
situating second conductor material on walls of the plugging resin and the second non-cylindrical hole;
using a flash plate step to increase a thickness of the second conductor material on the walls of the second non-cylindrical hole;
and bridging the second conductor material on the walls of the second non-cylindrical hole to fill the second non-cylindrical hole with conductor material.

### Claim 2 (depends on 1)

The method of claim 1, wherein ablating the core material includes ablating the core material on a first side to a partial depth of the core material to form a pattern of first holes to the partial depth and ablating the core material on a second side opposite the first side to form a pattern of second holes that mirrors the pattern of the first holes so as to create the non-cylindrical holes all the way through the core material.

### Claim 3 (depends on 2)

The method of claim 2, wherein situating the conductor material includes using an electroless plating process to situate the conductor material.

### Claim 4 (depends on 3)

The method of claim 3, further comprising roughening the conductor material to enhance an adhesion property of the conductor material.

### Claim 5 (depends on 4)

The method of claim 4, wherein roughening the conductor material includes using a black oxide to roughen the conductor material.

### Claim 6 (depends on 5)

The method of claim 5, further comprising grinding the plugging resin to remove excess resin out of the first non-cylindrical hole.

### Claim 7 (depends on 6)

The method of claim 6, wherein ablating the plugging resin includes ablating the plugging resin on a first side to a partial depth of the plugging resin to form a pattern of first holes to the partial depth and ablating the plugging resin on a second side opposite the first side to form a pattern of second holes that mirrors the pattern of the first holes so as to create the second non-cylindrical holes all the way through the plugging resin.

### Claim 8 (depends on 7)

The method of claim 7, wherein situating the second conductor material includes using an electroless plating process to situate the conductor material.

### Claim 9 (depends on 8)

The method of claim 8, further comprising roughening the second conductor material to enhance an adhesion property of the second conductor material.

### Claim 10 (depends on 9)

The method of claim 9, wherein roughening the second conductor material includes using a black oxide to roughen the conductor material.