# US 10,121,700 B2 · Semiconductor device and fabrication method thereof

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- Number: US 10,121,700 B2
- Document ID: US10121700B2
- Status: Granted
- Kind: B2
- Application number: 15/809,120
- Filed: 2017-11-10
- Published: 2018-05-10
- Granted: 2018-11-06
- Earliest claimed: 2016-11-10
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Yong Li
- Web page: https://patentgrep.com/patent/US10121700B2

## CPC

- H10W 20/049: {by diffusing alloying elements}
- H10D 30/0212: {using self-aligned silicidation}
- H10D 30/0213: {providing different silicide thicknesses on gate electrodes and on source regions or drain regions}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/0112: {using conductive layers comprising silicides}
- H10D 64/01125: {the silicides being formed by chemical reaction with the semiconductor after the contact hole formation}
- H10D 64/0131: {the additional conductive layer comprising a silicide layer formed by the silicidation reaction between the layer of silicon with a metal layer which is not formed by metal implantation}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 84/0137: {the gate conductors being silicided}
- H10D 84/0174: {the gate conductors being silicided}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 14/69215: {the material being a silicon oxide, e.g. SiO2}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/047: {by introducing additional elements therein}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10D 30/62: Fin field-effect transistors [FinFET]
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor devices and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming gate structures over the base substrate; forming doped source/drain regions in the base substrate at two sides of each of the gate structures; forming an oxide layer on each of the doped source/drain regions; forming a metal layer on the oxide layer; and performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions. The metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a base substrate;
forming gate structures over the base substrate;
forming doped source/drain regions in the base substrate at two sides of each of the gate structures;
forming an oxide layer on each of the doped source/drain regions;
forming a metal layer on the oxide layer; and
performing a reactive thermal annealing process, such that the metal layer reacts with a material of the oxide layer and a material of the doped source/drain regions to form a metal contact layer on each of the doped source/drain regions,
wherein the metal contact layer includes a first metal contact layer on the doped source/drain region, an oxygen-containing metal contact layer on the first metal contact layer, and a second metal contact layer on the oxygen-containing metal contact layer,
wherein the first metal contact layer is made of silicide, the oxygen-containing metal contact layer is made of oxysilicide, and the second metal contact layer is made of silicide.

### Claim 2 (depends on 1)

The method according to claim 1, wherein forming the oxide layer comprises:
performing an oxidation process on the doped source/drain regions.

### Claim 3 (depends on 2)

The method according to claim 2, wherein:
the oxidation process is a chemical soaking process.

### Claim 4 (depends on 3)

The method according to claim 3, wherein:
a mixture solution of sulfuric acid and hydrogen peroxide is used to perform the chemical soaking process to the doped source/drain regions;
a volume ratio of sulfuric acid and hydrogen peroxide in the mixture solution is in a range of approximately 1:1 to 1:5; and
a temperature of the mixture solution is in a range of approximately 120° C.-180° C.

### Claim 5 (depends on 3)

The method according to claim 3, wherein:
a mixture solution of ammonia and hydrogen peroxide is used to perform the chemical soaking process to the doped source/drain regions;
a volume ratio of ammonia and hydrogen peroxide in the mixture solution is in a range of approximately 1:4 to 1:15; and
a temperature of the mixture solution is in a range of approximately 25° C.-45° C.

### Claim 6 (depends on 3)

The method according to claim 3, wherein:
ozone-containing deionized water is used to perform the chemical soaking process.

### Claim 7 (depends on 1)

The method according to claim 1, wherein:
a thickness of the oxide layer is in a range of approximately 5 Å-30 Å.

### Claim 8 (depends on 1)

The method according to claim 1, wherein:
the metal layer is made of Ti.

### Claim 9 (depends on 8)

The method according to claim 8, wherein:
the first metal contact layer is made of titanium silicide;
the oxygen-containing metal contact layer is made of titanium oxysilicide; and
the second metal contact layer is made of titanium silicide.

### Claim 10 (depends on 1)

The method according to claim 1, before forming the oxide layers, further comprising:
forming a dielectric layer on a portion of the base substrate exposed by the gate structures and on the gate structures; and
etching the dielectric layer to form through-holes passing through the dielectric layer and exposing at least a portion of each of the doped source/drain regions,
wherein the through-holes expose the oxide layers on the doped source/drain regions.

### Claim 11 (depends on 10)

The method according to claim 10, wherein:
the metal layer is also formed on side surfaces of the through-holes and a top surface of the dielectric layer when forming the metal layer; and
the metal contact layers are formed on the doped source/drain regions exposed by the through-holes.

### Claim 12 (depends on 11)

The method according to claim 11, after forming the through-holes, further comprising:
forming a conductive plug filling the through-hole and electrically connected with the metal contact layer in each of the through-holes.

### Claim 13 (depends on 11)

The method according to claim 11, after forming the through-holes and before forming the conductive plugs, further comprising:
etching the dielectric layer to form openings exposing the gate structures in the dielectric layer; and
forming gate plugs filling the openings and electrically connected with the gate structures in the openings for forming the conductive plugs.

### Claim 14 (depends on 10)

The method according to claim 10, wherein the dielectric layer including an interlayer dielectric layer and a top dielectric layer above top surfaces of the gate structures, the interlayer dielectric layer leveling with or lower than the top surfaces of the gate structures, a gate-last process for forming the gate structures and the doped source/drain regions comprises:
forming dummy gate structures on the base substrate;
forming sidewall spacers on side surfaces of each of the dummy gate structures;
forming doped source/drain regions in the base substrate at two sides of each of the gate structures;
forming an interlayer dielectric layer exposing top surfaces of the gate structures and on a portion of the base substrate exposed by the dummy gate structures;
removing the dummy gate structures to form openings; and
forming a gate structure in each of the openings.

### Claim 15 (depends on 10)

The method according to claim 10, wherein a gate first process for forming the gate structures and the doped source/drain regions comprises:
forming gate structures on the base substrate;
forming sidewall spacers on side surfaces of each of the gate structures; and
forming doped source/drain regions in the base substrate at two sides of each of the gate structures.

### Claim 16 (depends on 1)

The method according to claim 1, after performing the reactive thermal annealing process, further comprising:
forming a dielectric layer on a portion of the base substrate exposed by the gate structures and on the gate structures;
etching through the dielectric layer to form through-holes passing through the dielectric layer and exposing surfaces of the second metal contact layers; and
forming a conductive plug in each of the through-holes to fill the through-holes.