# US 10,121,698 B2 · Method of manufacturing a semiconductor device

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- Number: US 10,121,698 B2
- Document ID: US10121698B2
- Status: Granted
- Kind: B2
- Application number: 15/407,145
- Filed: 2017-01-16
- Published: 2017-05-04
- Granted: 2018-11-06
- Earliest claimed: 2014-01-13
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company, Ltd.
- Inventors: Hsiang-Huan Lee; Shau-Lin Shue; Kuang-Kuo Koai; Hai-Ching Chen; Tung-Ching Tseng; Wen-Cheng Yang; Chung-En Kao; Ming-Han Lee; Hsin-Yen Huang
- Web page: https://patentgrep.com/patent/US10121698B2

## CPC

- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10P 14/22: using physical deposition, e.g. vacuum deposition or sputtering
- H10P 14/44: Physical vapour deposition [PVD]
- H10P 50/642: {Chemical etching}
- H10P 52/403: {of conductive or resistive materials}
- H10P 70/20: {Cleaning during device manufacture}
- H10P 70/23: {during, before or after processing of insulating materials}
- H10P 70/234: {the processing being the formation of vias or contact holes}
- H10P 72/0461: {characterised by the presence of two or more transfer chambers}
- H10P 72/0468: {comprising a chamber adapted to a particular process}
- H10P 72/30: for conveying, e.g. between different workstations
- H10P 72/3302: {Mechanical parts of transfer devices}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10W 20/042: {the barrier, adhesion or liner layers being seed or nucleation layers}
- H10W 20/0523: {by irradiating with ultraviolet or particle radiation}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/062: {by smoothing of conductive parts, e.g. by planarisation}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/095: {by irradiating with electromagnetic or particle radiation (plasma treatment H10W20/096)}
- H10W 20/097: {by thermally treating}
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10

## Abstract

Semiconductor device metallization systems and methods are disclosed. In some embodiments, a metallization system for semiconductor devices includes a mainframe, and a plurality of modules disposed proximate the mainframe. One of the plurality of modules comprises a physical vapor deposition (PVD) module and one of the plurality of modules comprises an ultraviolet light (UV) cure module.

## Claims

### Claim 1

A method of processing a semiconductor device, the method comprising:
in a first tool, depositing a low-k material on a workpiece;
in a second tool, etching the low-k material on the workpiece;
in a third tool, performing an ash and clean process on the workpiece; and
in a fourth tool having a plurality of modules:
performing an ultraviolet light cure process on the workpiece in a first module of the plurality of modules;
performing a K value recovery process on the workpiece in the first module;
removing moisture from the low-k material on the workpiece in the first module; and
performing a pre-clean process on the workpiece in the first module.

### Claim 2 (depends on 1)

The method of claim 1, further comprising partially curing the low-k material etching the low-k material.

### Claim 3 (depends on 1)

The method of claim 1, wherein the ultraviolet light cure process is performed at a temperature of about 200 degrees C. to about 400 degrees C., in the presence of an ambient gas of He, Ar, or N2, and at a pressure of about 0.1 Torr to about 10 Torr.

### Claim 4 (depends on 1)

The method of claim 1, wherein the K value recovery process is performed at a temperature of about 150 degrees C. to about 400 degrees C., in the presence of an ambient gas selected from the group consisting of He, Ar, N2, and carbon-containing silane, at a pressure of about 1 Torr to about 100 Torr.

### Claim 5 (depends on 4)

The method of claim 4, wherein the carbon-containing silane includes a chemical selected from the group consisting of CxHySi, CHyOzSi, CxHyNvSi, CxHyOzNvSi, and combinations thereof.

### Claim 6 (depends on 1)

The method of claim 1, wherein the removing of moisture from the low-k material includes subjecting the low-k material to a temperature of about 100 degrees C. to about 600 degrees C., in the presence of an ambient gas of Ar, He, N2, H2, NH3, O3, CO2, or O2, and at a pressure of about 0.1 Torr to about 10 Torr.

### Claim 7 (depends on 1)

The method of claim 1, wherein the pre-clean process is an ultraviolet pre-clean process.

### Claim 8 (depends on 1)

The method of claim 1, further comprising:
transporting the workpiece to a second module of the plurality of modules and depositing a barrier layer on the low-k material in the second module.

### Claim 9 (depends on 8)

The method of claim 8, further comprising transporting the workpiece to a third module and performing a barrier ultraviolet treatment on the barrier layer.

### Claim 10

A method comprising:
placing a semiconductor device in a metallization system, the semiconductor device comprising a low-k dielectric layer;
in a first module of the metallization system:
exposing the low-k dielectric layer to an ultraviolet (UV) light;
removing moisture and/or residual gas from the low-k dielectric layer; and
pre-cleaning the semiconductor device, wherein the exposing, the removing, and the pre-cleaning are completed without an air break in the first module;
in a second module of the metallization system, depositing a barrier layer on the low-k dielectric layer;
in the first module of the metallization system, purifying the barrier layer using a UV treatment; and
in a third module of the metallization system, depositing a seed layer on the barrier layer.

### Claim 11 (depends on 10)

The method of claim 10, wherein the exposing of the low-k dielectric layer to UV light fully cures the low-k dielectric layer.

### Claim 12 (depends on 10)

The method of claim 10, further comprising:
in a third module of the metallization system, depositing a metal on the seed layer.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
in a fourth module of the metallization system, performing a chemical mechanical polish on the metal.

### Claim 14 (depends on 10)

The method of claim 10, wherein the purifying of the barrier layer is performed at a temperature of about 100 degrees C. to about 600 degrees C., in the presence of an ambient gas of Ar, He, N2, H2, NH3, SiH4, or Ne, and at a pressure of about 0.1 Torr to about 10 Torr.

### Claim 15 (depends on 10)

The method of claim 10, wherein the exposing of the low-k dielectric layer to an ultraviolet (UV) light is performed at a temperature of about 200 degrees C. to about 400 degrees C., in the presence of an ambient gas of He, Ar, or N2, and at a pressure of about 0.1 Torr to about 10 Torr.

### Claim 16 (depends on 10)

The method of claim 10, further comprising exposing the low-k dielectric layer to a K value recovery process performed at a temperature of about 150 degrees C. to about 400 degrees C., in the presence of an ambient gas selected from the group consisting of He, Ar, N2, and carbon-containing silane, at a pressure of about 1 Torr to about 100 Torr.

### Claim 17

A method comprising:
depositing a dielectric layer on a workpiece;
etching openings in the dielectric layer;
ashing and cleaning the dielectric layer;
placing the workpiece in a metallization system;
at least partially curing the dielectric layer in a UV cure module of the metallization system;
performing a K value recovery process in the UV cure module after the at least partially curing the dielectric layer in the UV cure module;
depositing a barrier layer on the dielectric layer in a barrier module of the metallization system; and
depositing a seed layer on the barrier layer in a seed module of the metallization system.

### Claim 18 (depends on 17)

The method of claim 17, wherein the at least partially curing of the dielectric layer includes fully curing the dielectric layer.

### Claim 19 (depends on 17)

The method of claim 17, further comprising exposing the barrier layer to a UV barrier treatment in the UV cure module.

### Claim 20 (depends on 17)

The method of claim 17, further comprising performing a UV pre-clean in the UV cure module before the step of depositing a barrier layer.