# US 10,121,694 B2 · Methods of manufacturing a semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,694 B2 - Document ID: US10121694B2 - Status: Granted - Kind: B2 - Application number: 14/519,829 - Filed: 2014-10-21 - Published: 2016-02-04 - Granted: 2018-11-06 - Earliest claimed: 2014-07-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Company, Ltd. - Inventors: Yu-Jung Chang; Chin-Chang Hsu; Ying-Yu Shen; Nien-Yu Tsai; Wen-Ju Yang - Web page: https://patentgrep.com/patent/US10121694B2 ## CPC - H10W 20/46: comprising air gaps - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - H10W 20/072: {of dielectric parts comprising air gaps} - H10W 20/43: Layouts of interconnections - H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants - H10W 20/495: {Capacitive arrangements or effects of, or between wiring layers} - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - H10W 72/20: Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Methods of manufacturing a semiconductor device are described. In an embodiment, the method may include providing a substrate having a metal layer disposed thereon, the metal layer having a conductive trace pattern formed therein; depositing a dielectric material over the conductive trace pattern of the metal layer; determining a layout of a plurality of air gaps that will be formed in the dielectric material based on a design rule checking (DRC) procedure and the conductive trace pattern; and forming the plurality of air gaps in the dielectric material based on the layout of the plurality of air gaps. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, the method comprising: generating a first candidate air gap layout of an insulating layer from a conductive trace pattern, the first candidate air gap layout comprising a first plurality of parallel air gaps; generating a second candidate air gap layout of the insulating layer from the first candidate air gap layout, the second candidate air gap layout comprising the first plurality of parallel air gaps and a second plurality of parallel air gaps, each of the second plurality of parallel air gaps disposed between air gaps of the first plurality of parallel air gaps; selecting the first candidate air gap layout or the second candidate air gap layout as an air gap layout based on a design rule checking (DRC) procedure, the air gap layout being a layout of a plurality of air gaps disposed over the conductive trace pattern in the insulating layer that will be formed over the conductive trace pattern; and forming the insulating layer based on the air gap layout. ### Claim 2 (depends on 1) The method of claim 1, the forming the insulating layer comprising: depositing the insulating layer over the conductive trace pattern; and forming the plurality of air gaps in the insulating layer based on the air gap layout. ### Claim 3 (depends on 1) The method of claim 1, wherein the conductive trace pattern has a first pitch, and wherein a width of each of the first plurality of parallel air gaps is substantially equal to the first pitch. ### Claim 4 (depends on 3) The method of claim 3, wherein immediately adjacent air gaps of the first plurality of parallel air gaps are separated by a distance substantially equal to the first pitch. ### Claim 5 (depends on 3) The method of claim 3, wherein a width of each of the second plurality of parallel air gaps is substantially equal to the first pitch. ### Claim 6 (depends on 1) The method of claim 1, wherein the generating the first candidate air gap layout from the conductive trace pattern comprises: generating a polygon from the conductive trace pattern, the polygon being a boundary within which portions of the conductive trace pattern are routed; and generating the first plurality of parallel air gaps within the polygon. ### Claim 7 (depends on 1) The method of claim 1, wherein the first plurality of parallel air gaps extends in a direction substantially parallel to the conductive trace pattern. ### Claim 8 (depends on 1) The method of claim 1, wherein the selecting the first candidate air gap layout or the second candidate air gap layout as the air gap layout based on the DRC procedure comprises: performing the DRC procedure on the second candidate air gap layout; selecting the second candidate air gap layout as the air gap layout in case the second candidate air gap layout passes the DRC procedure; and selecting the first candidate air gap layout as the air gap layout in case the second candidate air gap layout fails the DRC procedure. ### Claim 9 A method of manufacturing a semiconductor device, the method comprising: providing a substrate having a metal layer disposed thereon, the metal layer having a conductive trace pattern formed therein; depositing a dielectric material layer over the conductive trace pattern of the metal layer; determining a layout of a plurality of air gaps that will be formed in the dielectric material layer based on a design rule checking (DRC) procedure and the conductive trace pattern comprising: generating a first candidate air gap layout comprising a first plurality of parallel air gaps within a boundary of the dielectric material layer; generating a second candidate air gap layout comprising the first plurality of parallel air gaps and a second plurality of parallel air gaps within the boundary, each of the second plurality of parallel air gaps disposed between air gaps of the first plurality of parallel air gaps; and selecting the first candidate air gap layout or the second candidate air gap layout as the layout of the plurality of air gaps based on the DRC procedure; and forming the plurality of air gaps in the dielectric material layer based on the layout of the plurality of air gaps. ### Claim 10 (depends on 9) The method of claim 9, wherein the determining the layout of the plurality of air gaps further comprises: before generating the first candidate air gap layout and the second candidate air gap layout, determining a boundary within which portions of the conductive trace pattern are routed; and after generating the second candidate air gap layout, performing the DRC procedure on the second candidate air gap layout. ### Claim 11 (depends on 9) The method of claim 9, wherein the selecting the first candidate air gap layout or the second candidate air gap layout comprises selecting the second candidate air gap layout as the layout of the plurality of air gaps in case the second candidate air gap layout passes the DRC procedure; and selecting the first candidate air gap layout as the layout of the plurality of air gaps in case the second candidate air gap layout fails the DRC procedure. ### Claim 12 (depends on 9) The method of claim 9, wherein the first plurality of parallel air gaps extends in a direction substantially parallel to the conductive trace pattern. ### Claim 13 (depends on 9) The method of claim 9, wherein the first plurality of parallel air gaps overlaps portions of the conductive trace pattern. ### Claim 14 (depends on 9) The method of claim 9, wherein the conductive trace pattern has a first pitch, and wherein a width of each of the first plurality of parallel air gaps is substantially equal to the first pitch. ### Claim 15 (depends on 14) The method of claim 14, wherein immediately adjacent air gaps of the first plurality of parallel air gaps are separated by a distance substantially equal to the first pitch. ### Claim 16 (depends on 14) The method of claim 14, wherein a width of each of the second plurality of parallel air gaps is substantially equal to the first pitch. ### Claim 17 A method of manufacturing a semiconductor device, the method comprising: determining a boundary of a region within which a conductive trace pattern is disposed; generating a first candidate air gap layout in an insulating layer based on the boundary, the first candidate air gap layout comprising a first plurality of parallel air gaps disposed within the boundary; generating a second candidate air gap layout in the insulating layer from the first candidate air gap layout, the second candidate air gap layout comprising the first plurality of parallel air gaps and a second plurality of parallel air gaps, each of the second plurality of parallel air gaps disposed between immediately adjacent air gaps of the first plurality of parallel air gaps; selecting the first candidate air gap layout or the second candidate air gap layout as a layout of air gaps that will be formed in the insulating layer over the conductive trace pattern; forming the insulating layer; and forming a plurality of air gaps in the insulating layer based on the layout of air gaps. ### Claim 18 (depends on 17) The method of claim 17, wherein the selecting is based on a design rule checking (DRC) procedure performed on the second candidate air gap layout, and wherein selecting comprises: selecting the second candidate air gap layout as the layout of air gaps in case the second candidate air gap layout passes the DRC procedure; and selecting the first candidate air gap layout as the layout of air gaps in case the second candidate air gap layout fails the DRC procedure. ### Claim 19 (depends on 17) The method of claim 17, wherein the conductive trace pattern has a first pitch, and wherein a width of each of the first plurality of parallel air gaps is substantially equal to the first pitch. ### Claim 20 (depends on 18) The method of claim 18, wherein the first plurality of parallel air gaps overlays portions of the conductive trace pattern.