# US 10,121,693 B2 · Semiconductor device and manufacturing method thereof

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- Number: US 10,121,693 B2
- Document ID: US10121693B2
- Status: Granted
- Kind: B2
- Application number: 15/727,671
- Filed: 2017-10-09
- Published: 2018-02-15
- Granted: 2018-11-06
- Earliest claimed: 2003-03-25
- Assignees: Renesas Electronics Corporation
- Applicants: Renesas Electronics Corporation
- Inventors: Junji Noguchi; Takayuki Oshima; Noriko Miura; Kensuke Ishikawa; Tomio Iwasaki; Kiyomi Katsuyama; Tatsuyuki Saito; Tsuyoshi Tamaru; Hizuru Yamaguchi
- Web page: https://patentgrep.com/patent/US10121693B2

## CPC

- H10W 20/087: {involving multiple stacked pre-patterned masks}
- H10W 20/031: {of conductive parts of the interconnections}
- H10W 20/033: {in openings in dielectrics}
- H10W 20/035: {combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers}
- H10W 20/037: {the barrier, adhesion or liner layers being on top of a main fill metal}
- H10W 20/056: {by filling conductive material into holes, grooves or trenches}
- H10W 20/071: {of dielectric parts thereof}
- H10W 20/075: {of multilayered thin functional dielectric layers}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/081: {by forming openings in the dielectric parts}
- H10W 20/084: {for dual-damascene structures}
- H10W 20/088: {involving partial etching of via holes}
- H10W 20/093: {by modifying materials of the dielectric parts}
- H10W 20/40: Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
- H10W 20/42: Vias, e.g. via plugs
- H10W 20/425: {Barrier, adhesion or liner layers}
- H10W 20/43: Layouts of interconnections
- H10W 20/4421: {the principal metal being copper}
- H10W 20/47: comprising two or more dielectric layers having different properties, e.g. different dielectric constants
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The reliability of wirings, each of which includes a main conductive film containing copper as a primary component, is improved. On an insulating film including the upper surface of a wiring serving as a lower layer wiring, an insulating film formed of a silicon carbonitride film having excellent barrier properties to copper is formed; on the insulating film, an insulating film formed of a silicon carbide film having excellent adhesiveness to a low dielectric constant material film is formed; on the insulating film, an insulating film formed of a low dielectric constant material as an interlayer insulating film is formed; and thereafter a wiring as an upper layer wiring is formed.

## Claims

### Claim 1

A semiconductor device comprising:
a semiconductor substrate;
a first insulating film formed over said semiconductor substrate;
a wiring opening formed in said first insulating film;
a wiring having a first conductive film containing copper as a primary component, and embedded in said wiring opening;
a second insulating film formed over said wiring and said first insulating film; and
a third insulating film formed over said second insulating film,
wherein a total stress of said second and third insulating films is −180 MPa or more.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1,
wherein said third insulating film relaxes a stress generated by said second insulating film.

### Claim 3 (depends on 1)

The semiconductor device according to claim 1,
wherein said second insulating film is a film generating a compression stress, and said third insulating film is a film generating a tensile stress.

### Claim 4 (depends on 1)

The semiconductor device according to claim 1,
wherein said second insulating film is made of a material containing silicon, carbon, and nitrogen.

### Claim 5 (depends on 1)

The semiconductor device according to claim 1,
wherein said third insulating film is made of silicon carbide.

### Claim 6 (depends on 1)

The semiconductor device according to claim 1,
wherein said second insulating film is a film generating a negative stress, and said third insulating film is a film generating a positive stress.

### Claim 7 (depends on 1)

The semiconductor device according to claim 1,
wherein said second insulating film is made of a material containing silicon and carbon and at least one of nitrogen and oxygen.

### Claim 8 (depends on 1)

The semiconductor device according to claim 1,
wherein a thickness of said second insulating film is 40 nm or less.

### Claim 9 (depends on 1)

The semiconductor device according to claim 1,
wherein a thickness of said third insulating film is 10 nm or less.

### Claim 10 (depends on 1)

The semiconductor device according to claim 1,
wherein said second insulating film has a function of restraining or preventing diffusion of copper; and
wherein said third insulating film has a function of controlling a stress of said second insulating film.

### Claim 11 (depends on 1)

The semiconductor device according to claim 1,
wherein said second insulating film is made of a material containing at least one of nitrogen and oxygen.