# US 10,121,691 B2 · Semiconductor substrate arrangements and a method for forming a semiconductor substrate arrangement

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- Number: US 10,121,691 B2
- Document ID: US10121691B2
- Status: Granted
- Kind: B2
- Application number: 15/040,540
- Filed: 2016-02-10
- Published: 2016-08-25
- Granted: 2018-11-06
- Earliest claimed: 2015-02-25
- Assignees: Infineon Technologies AG
- Applicants: Infineon Technologies AG
- Inventors: Peter Irsigler; Jens Peter Konrath; Hans-Joachim Schulze
- Web page: https://patentgrep.com/patent/US10121691B2

## CPC

- H10P 72/74: {using temporarily an auxiliary support}
- H10D 62/8325: {Silicon carbide}
- H10D 62/8503: {Nitride Group III-V materials, e.g. AlN or GaN}
- H10P 14/3208: {Silicon carbide}
- H10P 14/3216: {Nitrides}
- H10P 14/3242: {Structure}
- H10P 14/3408: {Silicon carbide}
- H10P 14/3416: {Nitrides}
- H10P 50/00: Etching of wafers, substrates or parts of devices
- H10P 50/646: {of Group III-V materials}
- H10P 90/00: Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
- H10P 90/1904: {Preparing vertically inhomogeneous wafers}
- H10P 72/7432: {used in a transfer process involving transfer directly from an origin substrate to a target substrate without use of an intermediate handle substrate}
- H10P 72/744: {Details of chemical or physical process used for separating the auxiliary support from a device or a wafer}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor substrate arrangement includes a carrier wafer and a plurality of semiconductor substrate pieces fixed to the carrier wafer and distributed laterally over the carrier wafer. The semiconductor substrate pieces of the plurality of semiconductor substrate pieces comprise a hexagonal shape.

## Claims

### Claim 1

A semiconductor substrate arrangement comprising:
a carrier wafer;
a plurality of semiconductor substrate pieces fixed to a front side of the carrier wafer, the plurality of semiconductor substrate pieces having a maximal lateral dimension, wherein the carrier wafer comprises a plurality of trenches in the front side of the carrier wafer,
wherein:
each distance between neighboring trenches of the plurality of trenches is less than the maximal lateral dimension of the semiconductor substrate pieces of the plurality of semiconductor substrate pieces; and
the plurality of semiconductor substrate pieces are a plurality of wide band-gap semiconductor substrate pieces; and
a grown semiconductor layer covering the semiconductor substrate pieces of the plurality of semiconductor substrate pieces and bridging gaps between neighboring edges of semiconductor substrate pieces of the plurality of semiconductor substrate pieces.

### Claim 2

A semiconductor substrate arrangement comprising:
a carrier wafer;
a plurality of semiconductor substrate pieces fixed to the carrier wafer, wherein the carrier wafer comprises at least one of the group of graphite and carbon; and
a grown semiconductor layer covering the semiconductor substrate pieces of the plurality of semiconductor substrate pieces and bridging gaps between neighboring edges of semiconductor substrate pieces of the plurality of semiconductor substrate pieces;
wherein:
the carrier wafer comprises a passivation layer covering at least a part of the carrier wafer, wherein the passivation layer comprises boron nitride; and
the plurality of semiconductor substrate pieces are a plurality of wide band-gap semiconductor substrate pieces.

### Claim 3 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the semiconductor substrate pieces of the plurality of semiconductor substrate pieces comprise a hexagonal shape.

### Claim 4 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the semiconductor substrate pieces of the plurality of semiconductor substrate pieces comprise a maximal lateral dimension of less than 1 cm.

### Claim 5 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the plurality of semiconductor substrate pieces comprises more than 10 semiconductor substrate pieces.

### Claim 6 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the plurality of semiconductor substrate pieces is a plurality of silicon carbide substrate pieces or a plurality of gallium nitride substrate pieces.

### Claim 7 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein a gap between neighboring edges of semiconductor substrate pieces of the plurality of semiconductor substrate pieces is less than 5 μm.

### Claim 8 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the semiconductor substrate pieces of the plurality of semiconductor substrate pieces are of substantially equal size and substantially equal shape.

### Claim 9 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein crystal directions of the semiconductor substrate pieces of the plurality of semiconductor substrate pieces are aligned to each other with a deviation of less than 5°.

### Claim 10 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein more than 70% of a surface of the carrier wafer is covered by the semiconductor substrate pieces of the plurality of semiconductor substrate pieces.

### Claim 11 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the carrier wafer comprises a diameter of more than 180 mm.

### Claim 12 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the carrier wafer is a high-melting material wafer having a melting point above 1800° C.

### Claim 13 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the carrier wafer comprises a non-circular shape.

### Claim 14 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the semiconductor substrate pieces of the plurality of semiconductor substrate pieces are distributed over the carrier wafer without lateral overlap.

### Claim 15 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein the carrier wafer comprises a passivation layer covering at least a part of the carrier wafer, wherein the passivation layer comprises boron nitride.

### Claim 16 (depends on 1)

The semiconductor substrate arrangement of claim 1, wherein each distance between neighboring trenches of the plurality of trenches is less than half the maximal lateral dimension of the semiconductor substrate pieces of the plurality of semiconductor substrate pieces.

### Claim 17

A semiconductor substrate arrangement comprising:
a carrier wafer;
a plurality of semiconductor substrate pieces fixed to a front side of the carrier wafer, wherein the carrier wafer comprises a plurality of trenches at the front side; and
a grown semiconductor layer covering the semiconductor substrate pieces of the plurality of semiconductor substrate pieces and bridging gaps between neighboring edges of semiconductor substrate pieces of the plurality of semiconductor substrate pieces;
wherein neighboring trenches of the plurality of trenches comprise a distance to each other of less than a maximal lateral dimension of the semiconductor substrate pieces of the plurality of semiconductor substrate pieces.

### Claim 18 (depends on 17)

The semiconductor substrate arrangement of claim 17, further comprising at least one epitaxial layer formed on the grown semiconductor layer covering the semiconductor substrate pieces.