# US 10,121,678 B2 · Method of manufacturing semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,121,678 B2 - Document ID: US10121678B2 - Status: Granted - Kind: B2 - Application number: 15/689,964 - Filed: 2017-08-29 - Published: 2018-03-01 - Granted: 2018-11-06 - Earliest claimed: 2016-08-31 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Hirokazu Saito; Takuya Hagiwara - Web page: https://patentgrep.com/patent/US10121678B2 ## CPC - H10P 50/71: {using masks for conductive or resistive materials} - H10P 14/68: Organic materials, e.g. photoresists - H10P 30/22: using masks - H10P 32/1406: {by ion implantation} - H10P 32/171: {being group IV material} - H10P 72/57: {Mask-wafer alignment} - H10P 76/204: {of organic photoresist masks} - H10P 76/405: {characterised by their composition, e.g. multilayer masks} - H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10 ## Abstract A method of manufacturing a semiconductor device includes forming a reference pattern in an inspection pattern formation region, forming a first mask layer over a semiconductor substrate, while forming a first inspection pattern in the inspection pattern formation region, and measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern. The method further includes implanting ions into the semiconductor substrate using a first mask layer, removing the first mask layer and the first inspection pattern and then forming a second mask layer over the semiconductor substrate, while forming a second inspection pattern in the inspection pattern formation region, and measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern. In plan view, the second inspection pattern is larger than the first inspection pattern and covers the entire region where the first inspection pattern is formed. ## Claims ### Claim 1 A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a MISFET formation region and an inspection pattern formation region in a main surface thereof; (b) embedding an insulating film in a trench formed in the main surface to form an isolation film, form first and second active regions each surrounded by the isolation film in the MISFET formation region, and form a reference pattern made of the isolation film in a first area in the inspection pattern formation region; (c) forming a first mask layer made of a first photoresist layer which covers the first active region and exposes the second active region in the MISFET formation region, while forming a first inspection pattern made of the first photoresist layer which covers a second area other than the first area and exposes a third area other than the first area in the inspection pattern formation region; (d) measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern; (e) ion-implanting a first impurity into the second active region exposed from the first mask layer in the MISFET formation region, while ion-implanting the first impurity into the third area exposed from the first inspection pattern in the inspection pattern formation region; (f) removing the first mask layer and the first inspection pattern; (g) forming a second mask layer made of a second photoresist layer which covers the second active region and exposes the first active region in the MISFET formation region, while forming a second inspection pattern made of the second photoresist layer which covers the second and third areas and exposes the first area in the inspection pattern formation region; and (h) measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern, wherein, in plan view, the second inspection pattern covers the entire second area where the first inspection pattern was formed to extend continuously from the second area to the third area. ### Claim 2 (depends on 1) The method of manufacturing the semiconductor device according to claim 1, wherein, in the step (e), a dose of the first impurity is not less than 1×1015 cm−2. ### Claim 3 (depends on 1) The method of manufacturing the semiconductor device according to claim 1, further comprising, after the step (h), the step of: (i) ion-implanting a second impurity into the first active region exposed from the second mask layer in the MISFET formation region, while ion-implanting the second impurity into the third area exposed from the second inspection pattern in the inspection pattern formation region. ### Claim 4 (depends on 1) The method of manufacturing the semiconductor device according to claim 1, wherein each of the first and second inspection patterns has a frame-like shape, and wherein a frame width of the second inspection pattern is larger than a frame width of the first inspection pattern. ### Claim 5 (depends on 4) The method of manufacturing the semiconductor device according to claim 4, wherein the reference pattern has a frame-like shape. ### Claim 6 (depends on 5) The method of manufacturing the semiconductor device according to claim 5, wherein each of the first and second inspection patterns is disposed inside the reference pattern. ### Claim 7 (depends on 5) The method of manufacturing the semiconductor device according to claim 5, wherein each of the first and second inspection patterns is disposed outside the reference pattern. ### Claim 8 (depends on 4) The method of manufacturing the semiconductor device according to claim 4, wherein each of the reference pattern and the first and second inspection patterns has a frame-like shape from which corner portions are removed. ### Claim 9 (depends on 8) The method of manufacturing the semiconductor device according to claim 8, wherein each of the first and second inspection patterns is disposed inside the reference pattern. ### Claim 10 (depends on 8) The method of manufacturing the semiconductor device according to claim 8, wherein each of the first and second inspection patterns is disposed outside the reference pattern. ### Claim 11 A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a MISFET formation region and an inspection pattern formation region in a main surface thereof; (b) embedding an insulating film in a trench formed in the main surface to form an isolation film, form first and second active regions each surrounded by the isolation film in the MISFET formation region, and form a reference pattern made of the isolation film in a first area in the inspection pattern formation region; (c) depositing a polysilicon film over the main surface of the semiconductor substrate; (d) forming a first mask layer made of a first photoresist layer which covers the first active region and exposes the second active region over the polysilicon film in the MISFET formation region, while forming a first inspection pattern made of the first photoresist layer which covers a second area other than the first area and exposes a third area other than the first area over the polysilicon film in the inspection pattern formation region; (e) measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern; (f) ion-implanting a first impurity into the polysilicon film over the second active region exposed from the first mask layer in the MISFET formation region, while ion-implanting the first impurity into the polysilicon film over the third area in the inspection pattern formation region; (g) removing the first mask layer and the first inspection pattern; (h) forming a second mask layer made of a second photoresist layer which covers the second active region and exposes the first active region over the polysilicon film in the MISFET formation region, while forming a second inspection pattern made of the second photoresist layer which covers the second and third areas and exposes the first area over the polysilicon film in the inspection pattern formation region; and (i) measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern, wherein, in plan view, the second inspection pattern covers the entire second area where the first inspection pattern was formed to extend continuously from the second area to the third area. ### Claim 12 (depends on 11) The method of manufacturing the semiconductor device according to claim 11, wherein, in the step (f), a dose of the first impurity is not less than 1×1015 cm−2. ### Claim 13 (depends on 11) The method of manufacturing the semiconductor device according to claim 11, further comprising, after the step (i), the step of: (j) ion-implanting a second impurity into the polysilicon film over the first active region exposed from the second mask layer in the MISFET formation region, while ion-implanting the second impurity into the polysilicon film over the third area in the inspection pattern formation region, wherein a conductivity type of the second impurity is opposite to a conductivity type of the first impurity. ### Claim 14 A method of manufacturing a semiconductor device, comprising the steps of: (a) providing a semiconductor substrate having a first MISFET formation region, a second MISFET formation region, and an inspection pattern formation region in a main surface thereof; (b) embedding an insulating film in a trench formed in the main surface to form an isolation film, form a first active region surrounded by the isolation film in the first MISFET formation region, form a second active region surrounded by the isolation film in the second MISFET formation region, and form a reference pattern made of the isolation film in a first area in the inspection pattern formation region; (c) forming a first gate electrode over the main surface in the first active region via a first gate insulating film, while forming a second gate electrode over the main surface in the second active region via a second gate insulating film; (d) forming a first mask layer made of a first photoresist layer which covers the first MISFET formation region and exposes the second MISFET formation region, while forming a first inspection pattern made of the first photoresist layer which covers a second area other than the first area and exposes a third area other than the first area in the inspection pattern formation region; (e) measuring a first amount of misalignment of the first inspection pattern with respect to the reference pattern; (f) ion-implanting a first impurity into the second active region exposed from the first mask layer, while ion-implanting the first impurity into the third area exposed from the first inspection pattern in the inspection pattern formation region; (g) removing the first mask layer and the first inspection pattern; (h) forming a second mask layer made of a second photoresist layer which covers the second MISFET formation region and exposes the first the MISFET formation region, while forming a second inspection pattern made of the second photoresist layer which covers the second and third areas and exposes the first area in the inspection pattern formation region; (i) measuring a second amount of misalignment of the second inspection pattern with respect to the reference pattern; and (j) ion-implanting a second impurity into the first active region exposed from the second mask layer, wherein, in plan view, the second inspection pattern covers the entire second area where the first inspection pattern was formed to extend continuously from the second area to the third area. ### Claim 15 (depends on 14) The method of manufacturing the semiconductor device according to claim 14, wherein, in the step (f), a dose of the first impurity is not less than 1×1015 cm−2. ### Claim 16 (depends on 14) The method of manufacturing the semiconductor device according to claim 14, further comprising, between the steps (c) and (d), the step of: (k) forming side-wall insulating films over respective side walls of the first and second gate electrodes. ### Claim 17 (depends on 14) The method of manufacturing the semiconductor device according to claim 14, wherein a conductivity type of the second impurity is opposite to a conductivity type of the first impurity.